Maulik V Vaghela has uploaded this change for review.
soc/intel/tigerlake: Update fsp params for Jasper Lake.
Update fsp parameters for Jasper Lake SoC.
Update fsp parameters for various configuration like Graphics, USB, xDCI,
PCI root ports etc.
These are the initial settings for JSL.
BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working
Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
---
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
2 files changed, 252 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38461/1
diff --git a/src/soc/intel/tigerlake/fsp_params_jsl.c b/src/soc/intel/tigerlake/fsp_params_jsl.c
index 6fb2f9f..3ac1f48 100644
--- a/src/soc/intel/tigerlake/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/fsp_params_jsl.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,9 +13,18 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
#include <fsp/api.h>
+#include <fsp/util.h>
+#include <fsp/ppi/mp_service_ppi.h>
#include <intelblocks/lpss.h>
+#include <intelblocks/mp_init.h>
+#include <intelblocks/xdci.h>
+#include <soc/intel/common/vbt.h>
+#include <soc/pci_devs.h>
#include <soc/ramstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
static const pci_devfn_t serial_io_dev[] = {
PCH_DEVFN_I2C0,
@@ -32,10 +41,139 @@
PCH_DEVFN_UART2
};
+static void parse_devicetree(FSP_S_CONFIG *params)
+{
+ const struct soc_intel_tigerlake_config *config;
+ config = config_of_soc();
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
+ params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
+ params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
+ params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
+ params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+ }
+
+ for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
+ params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+}
+
/* UPD parameters to be initialized before SiliconInit */
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
- /* TODO: Update with UPD override as FSP matures */
+ int i;
+ FSP_S_CONFIG *params = &supd->FspsConfig;
+
+ struct device *dev;
+ struct soc_intel_tigerlake_config *config;
+ config = config_of_soc();
+
+ /* Parse device tree and enable/disable devices */
+ parse_devicetree(params);
+
+ /* Load VBT before devicetree-specific config. */
+ params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+
+ /* Check if IGD is present and fill Graphics init param respectively */
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
+
+ if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+ params->PeiGraphicsPeimInit = 1;
+ else
+ params->PeiGraphicsPeimInit = 0;
+
+ /* Set USB OC pin to 0 first */
+ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++)
+ params->Usb2OverCurrentPin[i] = 0;
+
+ for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++)
+ params->Usb3OverCurrentPin[i] = 0;
+
+ /* Use coreboot MP PPI services if Kconfig is enabled */
+ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+ params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+ params->SkipMpInit = 0;
+ } else {
+ params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+ }
+
+ /* Override/Fill Fsp Silicon Param for mainboard */
+ mainboard_silicon_init_params(params);
+
+ /* Unlock upper 8 Bytes of RTC RAM */
+ params->RtcMemoryLock = 0;
+ params->PchLockDownBiosLock = 0x1;
+ params->PchPwrOptEnable = 0x1;
+
+ /* Legacy 8254 timer support */
+ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGatingOnS3 = 1;
+
+ /* disable Legacy PME */
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
+ /* USB configuration */
+ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
+
+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+ params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+ params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
+ params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+ params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
+
+ params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+ params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+ if (config->usb3_ports[i].tx_de_emp) {
+ params->Usb3HsioTxDeEmphEnable[i] = 1;
+ params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
+ }
+ if (config->usb3_ports[i].tx_downscale_amp) {
+ params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+ params->Usb3HsioTxDownscaleAmp[i] =
+ config->usb3_ports[i].tx_downscale_amp;
+ }
+ }
+
+ /* SDCard related configuration */
+ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5);
+ if (!dev)
+ params->ScsSdCardEnabled = 0;
+ else {
+ params->ScsSdCardEnabled = dev->enabled;
+ params->SdCardPowerEnableActiveHigh =
+ config->SdCardPowerEnableActiveHigh;
+ params->SdCardGpioCmdPadTermination = 0x1F;
+ }
+ params->Device4Enable = config->Device4Enable;
+
+ /* eMMC configuration */
+ dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0);
+ if (!dev)
+ params->ScsEmmcEnabled = 0;
+ else {
+ params->ScsEmmcEnabled = dev->enabled;
+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ }
+
+ /* Enable xDCI controller if enabled in devicetree and allowed */
+ dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
+ if (!xdci_can_enable())
+ dev->enabled = 0;
+ params->XdciEnable = dev->enabled;
+
+ /* Provide correct UART number for FSP debug logs */
+ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+}
+
+/* Mainboard GPIO Configuration */
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
/* Return list of SOC LPSS controllers */
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
index 810cff4..5cbcda9 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,10 +13,120 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
+#include <console/console.h>
#include <fsp/util.h>
+#include <soc/gpio_soc_defs.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
#include <soc/romstage.h>
+#include <soc/soc_chip.h>
+#include <string.h>
+
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
+ const struct soc_intel_tigerlake_config *config)
+{
+ unsigned int i;
+ const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ uint32_t mask = 0;
+
+ if (!dev || !dev->enabled) {
+ /*
+ * Skip IGD initialization in FSP if device
+ * is disable in devicetree.cb.
+ */
+ m_cfg->InternalGfx = 0;
+ m_cfg->IgdDvmt50PreAlloc = 0;
+ } else {
+ m_cfg->InternalGfx = 1;
+ /* Set IGD stolen size to 60MB. */
+ m_cfg->IgdDvmt50PreAlloc = 0xFE;
+ }
+
+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+ m_cfg->SaGv = config->SaGv;
+ m_cfg->RMT = config->RMT;
+
+ /* If Audio Codec is enabled, enable FSP UPD */
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
+ if (!dev)
+ m_cfg->PchHdaEnable = 0;
+ else
+ m_cfg->PchHdaEnable = dev->enabled;
+ for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
+ if (config->PcieRpEnable[i])
+ mask |= (1 << i);
+ }
+
+ m_cfg->PcieRpEnableMask = mask;
+
+ memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
+ sizeof(config->PcieClkSrcUsage));
+
+ for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) {
+ if (config->PcieClkSrcUsage[i] == 0)
+ m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
+ }
+
+ memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
+ sizeof(config->PcieClkSrcClkReq));
+
+ m_cfg->PrmrrSize = config->PrmrrSize;
+ m_cfg->EnableC6Dram = config->enable_c6dram;
+
+ /* Disable BIOS Guard */
+ m_cfg->BiosGuard = 0;
+
+ /* Disable Cpu Ratio Override temporary. */
+ m_cfg->CpuRatio = 0;
+ m_cfg->PcdDebugInterfaceFlags =
+ CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
+
+ /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
+ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+
+ m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
+
+ /* Audio */
+ m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
+ m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
+ m_cfg->PchHdaAudioLinkDmicEnable[0] = config->PchHdaAudioLinkDmicEnable[0];
+ m_cfg->PchHdaAudioLinkDmicEnable[1] = config->PchHdaAudioLinkDmicEnable[1];
+ for (i = 0; i < ARRAY_SIZE(config->PchHdaAudioLinkSspEnable); i++) {
+ m_cfg->PchHdaAudioLinkSspEnable[i] =
+ config->PchHdaAudioLinkSspEnable[i];
+ }
+ for (i = 0; i < ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable); i++) {
+ m_cfg->PchHdaAudioLinkSndwEnable[i] =
+ config->PchHdaAudioLinkSndwEnable[i];
+ }
+}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
- /* TODO: Update with UPD override as FSP matures */
+ const struct soc_intel_tigerlake_config *config;
+ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ config = config_of_soc();
+
+ soc_memory_init_params(m_cfg, config);
+
+ /* Enable SMBus controller based on config */
+ m_cfg->SmbusEnable = config->SmbusEnable;
+
+ /* Set debug probe type */
+ m_cfg->PlatformDebugConsent = config->DebugConsent;
+
+ /* Vt-D config */
+ m_cfg->VtdDisable = 0;
+
+ /* MbHob */
+ m_cfg->SkipMbpHob = 0;
+
+ mainboard_memory_init_params(mupd);
+}
+
+__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
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