[coreboot-gerrit] Patch set updated for coreboot: b1b9e4e exynos5420: Assign corect parent PLLs

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4469

-gerrit

commit b1b9e4e583a451b97fbd379e2b1f8ecc16e12119
Author: David Hendricks 
Date:   Mon Aug 12 14:52:45 2013 -0700

exynos5420: Assign corect parent PLLs

Assign correct parent PLL's for the following clocks:
    ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz)
    PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz)
    MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz)
    ACLK_266 (DPLL->MPLL) (300 -> 266MHz)
    ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz)
    ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz)
    ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz)
    MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz)
    MUX_MPHY_REFCLK (MPLL->OSC)
    MUX_UNIPRO (MPLL->OSC)
    MUX_MIPI1 (EPLL->OSC)
    MUX_DP1_EXT_VID (EPLL->OSC)
    MUX_FIMD1_OPT (EPLL->OSC)
    MUX_IPLL(IPLL->OSC)
    This also corrects the clock dividers for few of the clocks,
    as the clock parent changes affect the final frequency of the
    clocks.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/

Signed-off-by: David Hendricks

Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8
    Reviewed-on: https://gerrit.chromium.org/gerrit/65620
    Commit-Queue: Ronald G. Minnich 
    Reviewed-by: Ronald G. Minnich 
    Tested-by: Ronald G. Minnich 
---
 src/cpu/samsung/exynos5420/clock_init.c |  2 +-
 src/cpu/samsung/exynos5420/setup.h      | 17 +++++++++--------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index 8be286d..658b255 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -214,7 +214,7 @@ void system_clock_init(void)
    writel(CLK_DIV_G2D, &clk->clk_div_g2d);

writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu);
-	writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top6);
+	writel(CLK_SRC_TOP6_VAL, &clk->clk_src_top6);
    writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex);
    writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc);
 }
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index c2f69d2..794d4e1 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -225,18 +225,19 @@ struct exynos5_phy_control;
 #define CLK_DIV_CPU0_VAL	0x01440020

/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL	0x12222222
-#define CLK_SRC_TOP1_VAL	0x00100200
-#define CLK_SRC_TOP2_VAL	0x11101000
+#define CLK_SRC_TOP0_VAL	0x11101102
+#define CLK_SRC_TOP1_VAL	0x00200000
+#define CLK_SRC_TOP2_VAL	0x11101010
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111110
+#define CLK_SRC_TOP5_VAL	0x11111111
+#define CLK_SRC_TOP6_VAL	0x11110111
 #define CLK_SRC_TOP7_VAL	0x00022200

/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL	0x23713311
-#define CLK_DIV_TOP1_VAL	0x13100B00
-#define CLK_DIV_TOP2_VAL	0x11101100
+#define CLK_DIV_TOP0_VAL	0x22512211
+#define CLK_DIV_TOP1_VAL	0x13200900
+#define CLK_DIV_TOP2_VAL	0x11101110

/* APLL_LOCK */
 #define APLL_LOCK_VAL	(0x320)
@@ -439,7 +440,7 @@ struct exynos5_phy_control;
 #define CLK_DIV_ISP2_VAL        0x1

/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL	0x10666600
+#define CLK_SRC_DISP1_0_VAL	0x10006000
 #define CLK_DIV_DISP1_0_VAL	0x01050210

/*