[coreboot-gerrit] Change in coreboot[master]: riscv: update misaligned memory access exception handling

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27972 )

Change subject: riscv: update misaligned memory access exception handling
......................................................................

Patch Set 30:

(2 comments)

https://review.coreboot.org/#/c/27972/30/src/arch/riscv/misaligend.c
File src/arch/riscv/misaligend.c:

https://review.coreboot.org/#/c/27972/30/src/arch/riscv/misaligend.c@165
PS30, Line 165: 		if(EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
space required before the open parenthesis '('

https://review.coreboot.org/#/c/27972/30/src/arch/riscv/misaligend.c@165
PS30, Line 165: 		if(EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
trailing statements should be on next line