Angel Pons has uploaded this change for review.
sb/intel/lynxpoint/lpc.c: Follow Broadwell's order
Change-Id: Ibddac69297fd7ae901cde92d66e6c0485b526da1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/lynxpoint/lpc.c
1 file changed, 35 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47046/1
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 1845273..d1780fa 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -190,7 +190,6 @@
u16 reg16;
u32 reg32;
const char *state;
- u16 pmbase = get_pmbase();
int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
@@ -232,26 +231,6 @@
pci_write_config16(dev, GEN_PMCON_3, reg16);
printk(BIOS_INFO, "Set power %s after power failure.\n", state);
- /* Set up NMI on errors. */
- reg8 = inb(0x61);
- reg8 &= 0x0f; /* Higher Nibble must be 0 */
- reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
- // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
- reg8 |= (1 << 2); /* PCI SERR# Disable for now */
- outb(reg8, 0x61);
-
- reg8 = inb(0x70);
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- printk(BIOS_INFO, "NMI sources enabled.\n");
- reg8 &= ~(1 << 7); /* Set NMI. */
- } else {
- printk(BIOS_INFO, "NMI sources disabled.\n");
- reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
- }
- outb(reg8, 0x70);
-
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 &= ~(3 << 0); // SMI# rate 1 minute
@@ -275,6 +254,11 @@
/* SMI setup based on device tree configuration */
enable_alt_smi(config->alt_gp_smi_en);
}
+}
+
+static void pch_misc_init(struct device *dev)
+{
+ u16 pmbase = get_pmbase();
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); // PM1_CNT
@@ -282,12 +266,40 @@
reg32 |= (1 << 0); // SCI_EN
outl(reg32, pmbase + 0x04);
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ reg8 &= 0x0f; /* Higher Nibble must be 0 */
+ reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
+ // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
+ reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ printk(BIOS_INFO, "NMI sources enabled.\n");
+ reg8 &= ~(1 << 7); /* Set NMI. */
+ } else {
+ printk(BIOS_INFO, "NMI sources disabled.\n");
+ reg8 |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */
+ }
+ outb(reg8, 0x70);
+
+ /* Indicate DRAM init done for MRC S3 to know it can resume */
+ pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
+
+ /* Enable BIOS updates outside of SMM */
+ pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
+
/* Clear magic status bits to prevent unexpected wake */
RCBA32_OR(0x3310, (1 << 4) | (1 << 5) | (1 << 0));
reg16 = RCBA16(0x3f02);
reg16 &= ~0xf;
RCBA16(0x3f02) = reg16;
+
+ pch_enable_serial_irqs(dev);
}
/* LynxPoint PCH Power Management init */
@@ -461,18 +473,8 @@
apm_control(APM_CNT_ACPI_DISABLE);
}
-static void pch_disable_smm_only_flashing(struct device *dev)
-{
- printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
-
- pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
-}
-
static void pch_fixups(struct device *dev)
{
- /* Indicate DRAM init done for MRC S3 to know it can resume */
- pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
-
/*
* Enable DMI ASPM in the PCH
*/
@@ -488,14 +490,14 @@
/* IO APIC initialization. */
pch_enable_ioapic(dev);
- pch_enable_serial_irqs(dev);
-
/* Setup the PIRQ. */
pch_pirq_init(dev);
/* Setup power options. */
pch_power_options(dev);
+ pch_misc_init(dev);
+
/* Initialize power management */
if (pch_is_lp()) {
lpt_lp_pm_init(dev);
@@ -519,8 +521,6 @@
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
- pch_disable_smm_only_flashing(dev);
-
pch_set_acpi_mode();
pch_fixups(dev);
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