1 comment:
File src/soc/intel/xeon_sp/uncore.c:
uint16_t pci_err_inj_dis = pci_read_config16(dev, ERRINJCON);
if (!(pci_err_inj_dis & 1))
pci_update_config16(dev, ERRINJCON, 0xfffe, 1);
uint32_t dmircbar = pci_read_config32(dev, DMIRCBAR);
if (!(dmircbar & 1))
pci_update_config32(dev, DMIRCBAR, 0xfffe, 1);
OK, I think I know what you want to do:
/* Disable error injection */
pci_or_config16(dev, ERRINJCON, 1 << 0);
/*
* DMIRCBAR registers are not TXT lockable, but the BAR enable
* bit is. TXT requires that DMIRCBAR be disabled for security.
*/
pci_and_config32(dev, DMIRCBAR, ~(1 << 0));
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