Michał Żygowski has uploaded this change for review.
src/drivers/intel/fsp1_0: add option to specify MRC and ucode location
Change aims to give better control over CBFS content on FSP1.0 boards.
Specifying location of MRC cache and microcode will allow to save more
space in CBFS.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23e4e43bdddd7836ef74a2831e631d77599cdcca
---
M src/drivers/intel/fsp1_0/Kconfig
M src/drivers/intel/fsp1_0/Makefile.inc
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/30752/1
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig
index c7f6c18..6044c0e 100644
--- a/src/drivers/intel/fsp1_0/Kconfig
+++ b/src/drivers/intel/fsp1_0/Kconfig
@@ -89,6 +89,19 @@
should be a full sector of the flash ROM chip and nothing else should
be included in CBFS in any sector that the fast boot cache data is in.
+config MRC_CACHE_LOC
+ hex "MRC cache location in CBFS"
+ depends on ENABLE_MRC_CACHE && !MRC_CACHE_FMAP
+ help
+ Define the location of MRC cache data in CBFS.
+
+config CPU_MICROCODE_CBFS_LOC
+ hex "Microcode update base address in CBFS"
+ depends on CPU_MICROCODE_CBFS_GENERATE || CPU_MICROCODE_CBFS_EXTERNAL_HEADER
+ help
+ The location (base address) in CBFS that contains the
+ microcode update binary.
+
config VIRTUAL_ROM_SIZE
hex "Virtual ROM Size"
default ROM_SIZE
diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc
index 67741a9..4936022 100644
--- a/src/drivers/intel/fsp1_0/Makefile.inc
+++ b/src/drivers/intel/fsp1_0/Makefile.inc
@@ -44,6 +44,9 @@
mrc.cache-file := $(obj)/mrc.cache
mrc.cache-align := 0x10000
mrc.cache-type := mrc_cache
+ifneq ($(CONFIG_MRC_CACHE_LOC),)
+mrc.cache-COREBOOT-position := $(CONFIG_MRC_CACHE_LOC)
+endif
endif
endif
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