Ronak Kanabar uploaded patch set #16 to this change.

View Change

soc/intel/{icelake, tigerlake}: Remove DDI A lane programming

For newer Intel graphics(>10), The DDI port max lanes are set to 4 by
default. And kernel driver no longer relies on coreboot to provide
information via DDI_BUF_CTL_A(for DDI port A) register programming.
Hence removing this code.

BUG=b:150788968
BRANCH=None
TEST=checked jslrvp and tglrvp compilation and boot.

Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
---
M src/soc/intel/icelake/graphics.c
M src/soc/intel/tigerlake/graphics.c
2 files changed, 0 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39313/16

To view, visit change 39313. To unsubscribe, or for help writing mail filters, visit settings.