Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Patrick Rudolph.

Arthur Heymans uploaded patch set #2 to this change.

View Change

cpu/x86: Link page tables in stage if possible

When switching back and forward from 32 to 64, for example to call a
32bit FSP or toe call the payload, a new page tables in the respective
stage will be linked.

The advantages of this approach are:
- No need to determine a good place for page tables in cbfs that does
  not overlap.
- Works with non memory mapped flash (however all coreboot targets
  currently do support this)
- If later stages can use their own page tables which fits better with
  the vboot RO/RW flow

A disadvantage is that it increases the stage size. This could be
improved upon by used 1G pages and generating the pages at runtime.

TESTED on google/vilbox and qemu/q35: boots to payload

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562
---
M src/arch/x86/Kconfig
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/x86/64bit/Makefile.mk
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-q35/Kconfig
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/amd/picasso/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
14 files changed, 26 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/80337/2

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