Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55091 )
Change subject: mb/google/dedede/var/cret: Add ssfc codec cs42l42 support ......................................................................
mb/google/dedede/var/cret: Add ssfc codec cs42l42 support
Add cs42l42 codec support in cret.
BUG=b:189524295 TEST=Build and boot to check functional with cs42l42 EV board.
Signed-off-by: Dtrain Hsu dtrain_hsu@compal.corp-partner.google.com Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb 3 files changed, 35 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/55091/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e237b80..3f6a4ab 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -2,6 +2,7 @@ def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_CS42L42 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c index 5acef69..abe0c20 100644 --- a/src/mainboard/google/dedede/variants/cret/gpio.c +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -41,6 +41,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL ==> NC */ PAD_NC(GPP_H7, NONE), + /* H16 : AP_SUB_IO_L ==> HP_RST_ODL */ + PAD_CFG_GPO(GPP_H16, 1, PWROK), /* H17 : WWAN_RST_L */ PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* G0 : SD_CMD ==> NC */ diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 2586322..772bd96 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -1,3 +1,12 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 44 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_DA7219 1 + option AUDIO_CODEC_RT5682 2 + option AUDIO_CODEC_CS42l42 3 + end +end + chip soc/intel/jasperlake
# USB Port Configuration @@ -166,7 +175,29 @@ register "adc_1bit_rpt" = "1" register "micbias_lvl" = "2600" register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_DA7219 + end + end + chip drivers/i2c/cs42l42 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)" + register "ts_inv" = "true" + register "ts_dbnc_rise" = "RISE_DEB_1000_MS" + register "ts_dbnc_fall" = "FALL_DEB_0_MS" + register "btn_det_init_dbnce" = "100" + register "btn_det_event_dbnce" = "10" + register "bias_lvls[0]" = "15" + register "bias_lvls[1]" = "8" + register "bias_lvls[2]" = "4" + register "bias_lvls[3]" = "1" + register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" + device i2c 48 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_CS42l42 + end end end #I2C 4 device pci 1f.3 on