Subrata Banik has uploaded this change for review.
src/mainboard/{intel/google}: Include ASL for additional PCI segment
This patch allows mainboard to include static ASL for TBT PCI segment
extracted build/dsdt.aml
Device (PCI1)
{
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, One) // _SEG: PCI Segment
Name (_UID, One) // _UID: Unique ID
Name (_ADR, Zero) // _ADR: Address
....
}
Change-Id: I3601aa4e9002334fd80fc86ced9e1df2afc739b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/google/deltaur/dsdt.asl
M src/mainboard/google/volteer/dsdt.asl
M src/mainboard/intel/tglrvp/dsdt.asl
3 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41012/1
diff --git a/src/mainboard/google/deltaur/dsdt.asl b/src/mainboard/google/deltaur/dsdt.asl
index 631ec5e..6359feb 100644
--- a/src/mainboard/google/deltaur/dsdt.asl
+++ b/src/mainboard/google/deltaur/dsdt.asl
@@ -30,6 +30,9 @@
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
}
+#if CONFIG_PCI_SEGMENT_GROUPS > 1
+ #include <soc/intel/common/block/acpi/acpi/pcisegment.asl>
+#endif
}
/* Chrome OS specific */
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index a87c743..9a83359 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -33,6 +33,9 @@
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
}
+#if CONFIG_PCI_SEGMENT_GROUPS > 1
+ #include <soc/intel/common/block/acpi/acpi/pcisegment.asl>
+#endif
/* Mainboard hooks */
#include "mainboard.asl"
}
diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl
index c66e972..60275cc 100644
--- a/src/mainboard/intel/tglrvp/dsdt.asl
+++ b/src/mainboard/intel/tglrvp/dsdt.asl
@@ -29,6 +29,9 @@
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
}
+#if CONFIG_PCI_SEGMENT_GROUPS > 1
+ #include <soc/intel/common/block/acpi/acpi/pcisegment.asl>
+#endif
}
#if CONFIG(CHROMEOS)
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