Maulik V Vaghela uploaded patch set #2 to this change.

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soc/intel/tigerlake: Update fsp params for Jasper Lake.

Update fsp parameters for Jasper Lake SoC.
Update fsp parameters for various configuration like Graphics, USB, xDCI,
PCI root ports etc.

These are the initial settings for JSL.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
---
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
2 files changed, 239 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/38461/2

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