Patrick Rudolph would like Marcello Sylvester Bauer to review this change.
mb/lenovo: Add additional FMAPs on 8MiB devices
* Add FMAP for measured boot only, with a single RO partition.
* Add FMAP for measured boot only, with a single RO partition
but where the ME has been stripped.
Tested on X220 using VBOOT+measured boot:
* Used patched IFD and ME, boots into OS
Change-Id: I04c1add13198444638c669deec1e05159b1a09c9
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
A src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
A src/mainboard/lenovo/t420/vboot-ro.fmd
A src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
A src/mainboard/lenovo/t420s/vboot-ro.fmd
A src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
A src/mainboard/lenovo/t520/vboot-ro.fmd
A src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
A src/mainboard/lenovo/x220/vboot-ro.fmd
8 files changed, 176 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/39161/1
diff --git a/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
new file mode 100644
index 0000000..d1cbff7
--- /dev/null
+++ b/src/mainboard/lenovo/t420/vboot-ro-me_clean.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x20000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME
+ }
+ SI_BIOS 0x7e0000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t420/vboot-ro.fmd b/src/mainboard/lenovo/t420/vboot-ro.fmd
new file mode 100644
index 0000000..51df8a5
--- /dev/null
+++ b/src/mainboard/lenovo/t420/vboot-ro.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x500000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME 0x4ed000
+ }
+ SI_BIOS 0x300000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
new file mode 100644
index 0000000..d1cbff7
--- /dev/null
+++ b/src/mainboard/lenovo/t420s/vboot-ro-me_clean.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x20000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME
+ }
+ SI_BIOS 0x7e0000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t420s/vboot-ro.fmd b/src/mainboard/lenovo/t420s/vboot-ro.fmd
new file mode 100644
index 0000000..51df8a5
--- /dev/null
+++ b/src/mainboard/lenovo/t420s/vboot-ro.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x500000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME 0x4ed000
+ }
+ SI_BIOS 0x300000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
new file mode 100644
index 0000000..d1cbff7
--- /dev/null
+++ b/src/mainboard/lenovo/t520/vboot-ro-me_clean.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x20000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME
+ }
+ SI_BIOS 0x7e0000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/t520/vboot-ro.fmd b/src/mainboard/lenovo/t520/vboot-ro.fmd
new file mode 100644
index 0000000..51df8a5
--- /dev/null
+++ b/src/mainboard/lenovo/t520/vboot-ro.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x500000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME 0x4ed000
+ }
+ SI_BIOS 0x300000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
new file mode 100644
index 0000000..d1cbff7
--- /dev/null
+++ b/src/mainboard/lenovo/x220/vboot-ro-me_clean.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x20000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME
+ }
+ SI_BIOS 0x7e0000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x220/vboot-ro.fmd b/src/mainboard/lenovo/x220/vboot-ro.fmd
new file mode 100644
index 0000000..51df8a5
--- /dev/null
+++ b/src/mainboard/lenovo/x220/vboot-ro.fmd
@@ -0,0 +1,22 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL 0x500000 {
+ SI_DESC 0x1000
+ SI_GBE 0x2000
+ SI_ME 0x4ed000
+ }
+ SI_BIOS 0x300000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+
+ WP_RO {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_PADDING 0x7c0
+ RO_VPD(PRESERVE) 0x1000
+ GBB 0x1e000
+ COREBOOT(CBFS)
+ }
+ }
+}
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