[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/cannonlake: Remove ITSS IPC restore

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32174

Change subject: src/soc/intel/cannonlake: Remove ITSS IPC restore
......................................................................

src/soc/intel/cannonlake: Remove ITSS IPC restore

Remove ITSS IPC restore for cannonlake, as it does not take effect
since the ITSS PCR regsisters are locked post FSP-S.

Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.c
1 file changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32174/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index d50c689..845e9ef 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -24,7 +24,6 @@
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
 #include <soc/intel/common/vbt.h>
-#include <soc/itss.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>

@@ -168,19 +167,12 @@

void soc_init_pre_device(void *chip_info)
 {
-	/* Snapshot the current GPIO IRQ polarities. FSP is setting a
-	 * default policy that doesn't honor boards' requirements. */
-	itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
    /* Perform silicon specific init. */
    fsp_silicon_init(romstage_handoff_is_resume());

/* Display FIRMWARE_VERSION_INFO_HOB */
    fsp_display_fvi_version_hob();

-	/* Restore GPIO IRQ polarities back to previous settings. */
-	itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
-
    /* TODO(furquan): Get rid of this workaround once FSP is fixed. */
    cnl_configure_pads(NULL, 0);
 }