Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu, Yidi Lin.

Rex-BC Chen uploaded patch set #3 to this change.

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soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache

Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1
---
M src/soc/mediatek/mt8195/Makefile.inc
A src/soc/mediatek/mt8195/mmu_operations.c
M src/soc/mediatek/mt8195/soc.c
3 files changed, 34 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52925/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1
Gerrit-Change-Number: 52925
Gerrit-PatchSet: 3
Gerrit-Owner: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org>
Gerrit-Reviewer: Yidi Lin <yidi.lin@mediatek.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@mailbox.org>
Gerrit-Attention: Hung-Te Lin <hungte@chromium.org>
Gerrit-Attention: Paul Menzel <paulepanter@mailbox.org>
Gerrit-Attention: Yu-Ping Wu <yupingso@google.com>
Gerrit-Attention: Yidi Lin <yidi.lin@mediatek.com>
Gerrit-MessageType: newpatchset