Arthur Heymans has uploaded this change for review.

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sb/intel/lynxpoint: Setup gpio in bootblock

GPIO setup is needed for verstage. verstage can also still happen
after romstage so keep the GPIO init there too.

Change-Id: I448ca12f5ddab362983429c508e518b7042ef760
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
M src/mainboard/google/beltino/Makefile.inc
M src/mainboard/google/slippy/Makefile.inc
M src/mainboard/intel/baskingridge/Makefile.inc
M src/mainboard/supermicro/x10slm-f/Makefile.inc
M src/southbridge/intel/common/Makefile.inc
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/pch.h
10 files changed, 22 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36712/1
diff --git a/src/mainboard/asrock/h81m-hds/Makefile.inc b/src/mainboard/asrock/h81m-hds/Makefile.inc
index de18bc5..3fc7ac7 100644
--- a/src/mainboard/asrock/h81m-hds/Makefile.inc
+++ b/src/mainboard/asrock/h81m-hds/Makefile.inc
@@ -16,4 +16,5 @@

romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += gpio.c
bootblock-y += bootblock.c
diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc
index 7535350..0ecb31d 100644
--- a/src/mainboard/google/beltino/Makefile.inc
+++ b/src/mainboard/google/beltino/Makefile.inc
@@ -23,5 +23,7 @@
romstage-y += variants/$(VARIANT_DIR)/led.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c

+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc
index f80dcab..e35f93e 100644
--- a/src/mainboard/google/slippy/Makefile.inc
+++ b/src/mainboard/google/slippy/Makefile.inc
@@ -23,6 +23,8 @@
romstage-y += variants/$(VARIANT_DIR)/romstage.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c

+bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+
subdirs-y += variants/$(VARIANT_DIR)

ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc
index 91a7963..8f12999 100644
--- a/src/mainboard/intel/baskingridge/Makefile.inc
+++ b/src/mainboard/intel/baskingridge/Makefile.inc
@@ -17,6 +17,7 @@
ramstage-y += chromeos.c
verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c

+bootblock-y += gpio.c
romstage-y += gpio.c

smm-y += mainboard_smi.c
diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm-f/Makefile.inc
index 301070b..0b4f367 100644
--- a/src/mainboard/supermicro/x10slm-f/Makefile.inc
+++ b/src/mainboard/supermicro/x10slm-f/Makefile.inc
@@ -15,4 +15,5 @@
##

romstage-y += gpio.c
+bootblock-y += gpio.c
bootblock-y += bootblock.c
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 5ca7daf..433a310 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -34,6 +34,7 @@
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c

+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index e53ed8d..bacaf74 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -50,6 +50,7 @@
romstage-y += rcba.c pmutil.c

ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+bootblock-y += lp_gpio.c
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c
smm-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 39e6925..abcb35b 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -16,6 +16,7 @@
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "pch.h"
+#include "lp_gpio.h"

/*
* Enable Prefetching and Caching.
@@ -33,14 +34,6 @@
pci_write_config8(dev, 0xdc, reg8);
}

-
-static void map_rcba(void)
-{
- pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
-
- pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-}
-
static void enable_port80_on_lpc(void)
{
/* Enable port 80 POST on LPC. The chipset does this by default,
@@ -72,7 +65,7 @@

void bootblock_early_southbridge_init(void)
{
- map_rcba();
+ pch_enable_bars();
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
@@ -83,3 +76,12 @@
pch_enable_lpc();
mainboard_config_superio();
}
+
+void bootblock_southbridge_init(void)
+{
+#if CONFIG(INTEL_LYNXPOINT_LP)
+ setup_pch_lp_gpios(mainboard_gpio_map);
+#else
+ setup_pch_gpios(mainboard_gpio_map);
+#endif
+}
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index b49d3cf..9cf021e 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -45,7 +45,7 @@
return id == PCH_TYPE_LPT_LP;
}

-static void pch_enable_bars(void)
+void pch_enable_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 8802be1..561c5b7 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -184,6 +184,7 @@
int early_pch_init(const struct rcba_config_instruction *rcba_config);
void pch_enable_lpc(void);
void mainboard_config_superio(void);
+void pch_enable_bars(void);

#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I448ca12f5ddab362983429c508e518b7042ef760
Gerrit-Change-Number: 36712
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan@corrick.kiwi>
Gerrit-MessageType: newchange