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Documentation: add Gigabyte P34G v2

Change-Id: Ie8025f7bf4e7b40810c97a0b5fa80fd7c41e97eb
Signed-off-by: Daniel Maslowski <info@orangecms.org>
---
A Documentation/mainboard/gigabyte/p34g-v2.md
A Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
M Documentation/mainboard/index.md
3 files changed, 89 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/36010/1
diff --git a/Documentation/mainboard/gigabyte/p34g-v2.md b/Documentation/mainboard/gigabyte/p34g-v2.md
new file mode 100644
index 0000000..4dfcf79
--- /dev/null
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@@ -0,0 +1,88 @@
+# Gigabyte P34G v2
+
+This page describes how to run coreboot on the [Gigabyte P34G v2 gaming
+laptop](https://www.gigabyte.com/Laptop/P34G-v2).
+
+Original board name: GA-R3456R
+
+Rebrands:
+- Schenker XMG C404
+
+## Technology
+
+```eval_rst
++------------------+----------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/haswell/index` |
++------------------+----------------------------------------------+
+| Southbridge | Lynx Point |
++------------------+----------------------------------------------+
+| CPU | i7-4710HQ |
++------------------+----------------------------------------------+
+| EC / SuperIO | ITE IT8587E |
++------------------+----------------------------------------------+
+| Coprocessor | Intel ME, `me_cleaner` untested |
++------------------+----------------------------------------------+
+| TPM | None, but socket exists (see photo below) |
++------------------+----------------------------------------------+
+```
+
+## Required proprietary blobs
+
+```eval_rst
+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
+```
+
+## Flash chip
+
+![SPI chip and TPM location](p34g-v2_tpm_socket_spi_chip.jpg)
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | No |
++---------------------+------------+
+| Model | MX25L6406E |
++---------------------+------------+
+| Size | 8 MiB |
++---------------------+------------+
+| In circuit flashing | Yes |
++---------------------+------------+
+| Package | SOIC-8 |
++---------------------+------------+
+| Write protection | No |
++---------------------+------------+
+| Internal flashing | Untested |
++---------------------+------------+
+```
+
+## Flash layout
+
+```txt
+00000000:00000fff fd
+00400000:007fffff bios
+00001000:003fffff me
+```
+
+## EC firmware
+
+There is an additional 128KiB EC firmware blob within the BIOS region at
+`0x700000`. The EC has its own internal EPROM though, for which Gigabyte offers
+updates in a bundle with the UEFI firmware updates based on AMI Aptio. The EC
+firmware can be updated via AFU. An unmodified EC firmware version F005 seems
+to work fine with coreboot even without the extra 128KiB part. It could be
+extracted from a firmware update through `dd` etc and reinserted though. Other
+version have not been tested.
+
+## Known issues
+
+- EC / ACPI
+ * no suspend on LID close
+ * eject, sleep, backlight up/down, external screen buttons do not work
+ * Bluetooth LED shows inverted state, does not turn on on first press
+ * battery state can not be queried
+- CPU overheats on high load leading to force poweroff
+
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
diff --git a/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
new file mode 100644
index 0000000..9835a8a
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+++ b/Documentation/mainboard/gigabyte/p34g-v2_tpm_socket_spi_chip.jpg
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 83189757..f0f8f8e 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -40,6 +40,7 @@
## Gigabyte

- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
+- [P34G v2](gigabyte/p34g-v2.md)

## Google


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