Patrick Georgi submitted this change.

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Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
mb/gigabyte/ga-h61m-s2pv: Correct PCIe port setup

Coalescing is not needed, as root port #1 is enabled. Also, update the
comments to look more like the other two variants. Note that the Intel
H61 PCH only has six root ports, so devices 1c.6 and 1c.7 do not exist.

Change-Id: I3f4bf99ceec6c77f6e1eabea9b712245afee7d34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39742
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
index 08abc3e..b76200b 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb
@@ -34,7 +34,6 @@
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x003c0a01"
- register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
@@ -46,14 +45,14 @@
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio Audio controller
- device pci 1c.0 on end # PCIe x1 Port (PCIEX1)
- device pci 1c.1 off end # Unused PCIe Port
- device pci 1c.2 off end # Unused PCIe Port
- device pci 1c.3 off end # Unused PCIe Port
- device pci 1c.4 on end # Realtek RTL8111F Ethernet Controller
- device pci 1c.5 on end # ITE IT8892F PCIe to PCI bridge
- device pci 1c.6 off end # Unused PCIe Port
- device pci 1c.7 off end # Unused PCIe Port
+
+ device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1)
+ device pci 1c.1 off end # RP #2:
+ device pci 1c.2 off end # RP #3:
+ device pci 1c.3 off end # RP #4:
+ device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC
+ device pci 1c.5 on end # RP #6: ITE IT8892F PCIe to PCI bridge
+
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3f4bf99ceec6c77f6e1eabea9b712245afee7d34
Gerrit-Change-Number: 39742
Gerrit-PatchSet: 5
Gerrit-Owner: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged