Arthur Heymans has uploaded this change for review.
soc/intel/braswell: Use common cpu/intel/car code
The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.
A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).
Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/include/fsp/car.h
M src/soc/intel/braswell/romstage/Makefile.inc
4 files changed, 29 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32963/1
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc
index f50641e..e2bc852 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -117,35 +117,33 @@
* mm1: high 32-bits of TSC value
*/
+ /* coreboot assumes stack/heap region will be zero */
+ cld
+ movl %ecx, %edi
+ neg %ecx
+ /* Clear up to Temp Ram top. */
+ add %edx, %ecx
+ shrl $2, %ecx
+ xorl %eax, %eax
+ rep stosl
+
+ /* Need to align stack to 16 bytes at call instruction. Account for
+ the pushes below. */
+ andl $0xfffffff0, %esp
+ subl $8, %esp
+
/* Create cache_as_ram_params on stack */
- pushl %edx /* bootloader CAR end */
- pushl %ecx /* bootloader CAR begin */
- pushl %ebp /* FSP_INFO_HEADER */
pushl %edi /* bist */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
movd %mm0, %eax
pushl %eax /* tsc[31:0] */
- pushl %esp /* pointer to cache_as_ram_params */
-
- /* Save FSP_INFO_HEADER location in ebx */
- mov %ebp, %ebx
-
- /* coreboot assumes stack/heap region will be zero */
- cld
- movl %ecx, %edi
- neg %ecx
- /* Only clear up to current stack value. */
- add %esp, %ecx
- shrl $2, %ecx
- xorl %eax, %eax
- rep stosl
before_romstage:
post_code(0x2A)
/* Call cache_as_ram_main(struct cache_as_ram_params *) */
- call cache_as_ram_main
+ call bootblock_c_entry_bist
movb $0x69, %ah
jmp .Lhlt
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 2202121..f5faf72 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -94,66 +94,6 @@
run_postcar_phase(&pcf);
}
-/* This is the romstage C entry for platforms without
- CONFIG_C_ENVIRONMENT_BOOTBLOCK */
-asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params)
-{
- int i;
- const int num_guards = 4;
- const u32 stack_guard = 0xdeadbeef;
- u32 *stack_base;
- u32 size;
-
- /* Size of unallocated CAR. */
- size = _car_region_end - _car_relocatable_data_end;
- size = ALIGN_DOWN(size, 16);
-
- stack_base = (u32 *)(_car_region_end - size);
-
- for (i = 0; i < num_guards; i++)
- stack_base[i] = stack_guard;
-
- /* Initialize timestamp book keeping only once. */
- timestamp_init(car_params->tsc);
-
- /* Call into pre-console init code then initialize console. */
- car_soc_pre_console_init();
- car_mainboard_pre_console_init();
- console_init();
-
- printk(BIOS_DEBUG, "FSP TempRamInit successful\n");
-
- printk(BIOS_SPEW, "bist: 0x%08x\n", car_params->bist);
- printk(BIOS_SPEW, "tsc: 0x%016llx\n", car_params->tsc);
-
- display_mtrrs();
-
- if (car_params->bootloader_car_start != CONFIG_DCACHE_RAM_BASE
- || car_params->bootloader_car_end != (CONFIG_DCACHE_RAM_BASE
- + CONFIG_DCACHE_RAM_SIZE)) {
- printk(BIOS_INFO, "CAR mismatch: %08x--%08x vs %08lx--%08lx\n",
- CONFIG_DCACHE_RAM_BASE,
- CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE,
- (long)car_params->bootloader_car_start,
- (long)car_params->bootloader_car_end);
- }
-
- car_soc_post_console_init();
- car_mainboard_post_console_init();
-
- cache_as_ram_stage_main(car_params->fih);
-
- /* Check the stack. */
- for (i = 0; i < num_guards; i++) {
- if (stack_base[i] == stack_guard)
- continue;
- printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
- }
-
- /* we don't return here */
- platform_enter_postcar();
-}
-
/* This is the romstage C entry for platforms with
CONFIG_C_ENVIRONMENT_BOOTBLOCK */
void mainboard_romstage_entry(unsigned long bist)
@@ -172,6 +112,18 @@
fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
}
+ if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) {
+ /* Call into pre-console init code then initialize console. */
+ car_soc_pre_console_init();
+ car_mainboard_pre_console_init();
+ console_init();
+
+ display_mtrrs();
+
+ car_soc_post_console_init();
+ car_mainboard_post_console_init();
+ }
+
cache_as_ram_stage_main(fih);
}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index c051392..8d7a683 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -20,17 +20,6 @@
#include <fsp/api.h>
#include <stdint.h>
-/* cache-as-ram support for FSP 1.1. */
-struct cache_as_ram_params {
- uint64_t tsc;
- uint32_t bist;
- FSP_INFO_HEADER *fih;
- uintptr_t bootloader_car_start;
- uintptr_t bootloader_car_end;
-};
-
-/* Entry points from the cache-as-ram assembly code. */
-asmlinkage void cache_as_ram_main(struct cache_as_ram_params *car_params);
/* Per stage calls from the above two functions. The void * return from
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc
index c3ed415..b9c46b0 100644
--- a/src/soc/intel/braswell/romstage/Makefile.inc
+++ b/src/soc/intel/braswell/romstage/Makefile.inc
@@ -1,3 +1,4 @@
+romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += early_spi.c
romstage-y += pmc.c
romstage-y += romstage.c
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