John Su has uploaded this change for review.
mb/google/drallion: Update IA VR TDC current limit
Since Drallion is run CML U platform use baseline CPU
and follow b:148912093#comment1.
Change IA TDC value from 58w to 48w.
BUG=b:148912093
BRANCH=None
TEST=build coreboot and checked IA_TDC from TAT tool.
Change-Id: I5a80fb4fd0a9bd9bc343c1c0c7b47bb947fca226
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
---
M src/mainboard/google/drallion/ramstage.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/38718/1
diff --git a/src/mainboard/google/drallion/ramstage.c b/src/mainboard/google/drallion/ramstage.c
index 3855045..40a0faf 100644
--- a/src/mainboard/google/drallion/ramstage.c
+++ b/src/mainboard/google/drallion/ramstage.c
@@ -21,11 +21,33 @@
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
#define VPD_KEY_SYSTEM_SERIAL "serial_number"
#define VPD_KEY_MAINBOARD_SERIAL "mlb_serial_number"
#define VPD_SERIAL_LEN 64
+/* Thermal Design Current current limit. 0-4095 in 1/8A units. 1000 = 125A */
+#define VR_CFG_TDC(i) (uint16_t)((i) * 8)
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ config_t *cfg = config_of_soc();
+ static uint16_t mch_id = 0;
+
+ if (!mch_id) {
+ struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
+ }
+ /* IA TDC current limit is 48A for baseline U42 and U62 */
+ if ((mch_id == PCI_DEVICE_ID_INTEL_CML_ULT) || (mch_id == PCI_DEVICE_ID_INTEL_CML_ULT_6_2)) {
+ if (cfg->cpu_pl2_4_cfg == baseline)
+ /* TdcPowerLimit[1] = IA TDC current limit */
+ params->TdcPowerLimit[1] = VR_CFG_TDC(48);
+ }
+}
+
const char *smbios_system_serial_number(void)
{
static char serial[VPD_SERIAL_LEN];
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