Arthur Heymans has uploaded this change for review.
sb/intel/common/smihandler.c: Add common gnvs update mechanism
With common save state handling there is no need for per southbridge
handling.
Change-Id: I9dc0258f1335c678f992e8ad83f96b73fc474ec8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/common/pmutil.h
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/i82801gx/smihandler.c
M src/southbridge/intel/i82801ix/smihandler.c
M src/southbridge/intel/i82801jx/smihandler.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/lynxpoint/smihandler.c
8 files changed, 12 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/45476/1
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 8af1428..e24a53e 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -184,18 +184,6 @@
xhci_sleep(slp_type);
}
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
-{
- em64t101_smm_state_save_area_t *state =
- smi_apmc_find_state_save(apm_cnt);
- if (state) {
- /* EBX in the state save contains the GNVS pointer */
- gnvs = (struct global_nvs *)((u32)state->rbx);
- *smm_done = 1;
- printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
- }
-}
-
void southbridge_finalize_all(void)
{
intel_me_finalize_smm();
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 52b83dd..c71ff0b 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -130,7 +130,6 @@
void southbridge_smm_xhci_sleep(u8 slp_type);
void gpi_route_interrupt(u8 gpi, u8 mode);
void southbridge_gate_memory_reset(void);
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done);
void southbridge_finalize_all(void);
void southbridge_smi_monitor(void);
em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index ff61c6f..cb42832 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -8,7 +8,7 @@
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
-#include <cpu/intel/em64t101_save_state.h>
+#include <cpu/x86/save_state.h>
#include <elog.h>
#include <halt.h>
#include <option.h>
@@ -268,7 +268,13 @@
"SMI#: SMM structures already initialized!\n");
return;
}
- southbridge_update_gnvs(reg8, &smm_initialized);
+ int node = get_apmc_node(reg8);
+
+ if (node >= 0) {
+ if (!get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs)))
+ smm_initialized = 1;
+ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
+ }
break;
case APM_CNT_FINALIZE:
if (mainboard_finalized) {
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 562dae3..fa91c37 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -21,10 +21,6 @@
u16 pmbase = DEFAULT_PMBASE;
u8 smm_initialized = 0;
-/* This implementation was removed since it was invalid. There will be one shared
- approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 699f51f..3ca507f 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -14,10 +14,6 @@
struct global_nvs *gnvs;
#endif
-/* This implementation was removed since it was invalid. There will be one shared
- approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c
index 16ec025..f5e9b75 100644
--- a/src/southbridge/intel/i82801jx/smihandler.c
+++ b/src/southbridge/intel/i82801jx/smihandler.c
@@ -15,10 +15,6 @@
u16 pmbase = DEFAULT_PMBASE;
u8 smm_initialized = 0;
-/* This implementation was removed since it was invalid. There will be one shared
- approach to set GNVS pointer into SMM without the 0xEA PM Trap mentioned above. */
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) { }
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 2bc31cf..5bf18c9 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -145,18 +145,6 @@
#undef IOTRAP
}
-void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
-{
- em64t101_smm_state_save_area_t *state =
- smi_apmc_find_state_save(apm_cnt);
- if (state) {
- /* EBX in the state save contains the GNVS pointer */
- gnvs = (struct global_nvs *)((u32)state->rbx);
- *smm_done = 1;
- printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
- }
-}
-
void southbridge_finalize_all(void)
{
intel_me_finalize_smm();
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index a033d68..007b383 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -221,7 +221,7 @@
static void southbridge_smi_apmc(void)
{
u8 reg8;
- em64t101_smm_state_save_area_t *state;
+ int node;
static int chipset_finalized = 0;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -269,10 +269,10 @@
"SMI#: SMM structures already initialized!\n");
return;
}
- state = smi_apmc_find_state_save(reg8);
- if (state) {
+ node = get_apmc_node(reg8);
+ if (node >= 0) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (struct global_nvs *)((u32)state->rbx);
+ get_save_state_reg(RBX, node, &gnvs, sizeof(gnvs));
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
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