HAOUAS Elyes has uploaded this change for review.

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mb/mb899: Move superio devices define to 'w83627ehg.h'

Change-Id: Ib2c30c52ee23ae6c9df67b4cdc16faf3e1eaeb68
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/mainboard/ibase/mb899/Kconfig
M src/mainboard/ibase/mb899/early_init.c
M src/superio/winbond/w83627ehg/w83627ehg.h
3 files changed, 33 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37630/1

diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index d93121d..562cd2e 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -32,6 +32,10 @@
 	int
 	default 4
 
+config SUPERIO_ADDRESS
+	hex
+	default 0x4e
+
 config VGA_BIOS_FILE
 	string
 	default "amipci_01.20"
diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c
index 0b00502..bea43bb 100644
--- a/src/mainboard/ibase/mb899/early_init.c
+++ b/src/mainboard/ibase/mb899/early_init.c
@@ -23,9 +23,6 @@
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
 
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-#define SUPERIO_DEV PNP_DEV(0x4e, 0)
-
 /* This box has one superio
  * Also set up the GPIOs from the beginning. This is the "no schematic
  * but safe anyways" method.
@@ -45,14 +42,14 @@
 	pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
 	pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
 
-	dev = PNP_DEV(0x4e, W83627EHG_SP1);
+	dev = W83627EHG_SP1_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
 	pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
 	pnp_set_enable(dev, 1);
 
-	dev = PNP_DEV(0x4e, W83627EHG_SP2);
+	dev = W83627EHG_SP2_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
@@ -60,7 +57,7 @@
 	// pnp_write_config(dev, 0xf1, 4); // IRMODE0
 	pnp_set_enable(dev, 1);
 
-	dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
+	dev = W83627EHG_KBC_DEV; // Keyboard
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
@@ -68,27 +65,27 @@
 	//pnp_write_config(dev, 0xf0, 0x82);
 	pnp_set_enable(dev, 1);
 
-	dev = PNP_DEV(0x4e, W83627EHG_GPIO2);
+	dev = W83627EHG_GPIO2_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 1); // Just enable it
 
-	dev = PNP_DEV(0x4e, W83627EHG_GPIO3);
+	dev = W83627EHG_GPIO3_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 	pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 	pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 
-	dev = PNP_DEV(0x4e, W83627EHG_FDC);
+	dev = W83627EHG_FDC_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 
-	dev = PNP_DEV(0x4e, W83627EHG_PP);
+	dev = W83627EHG_PP_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 
 	/* Enable HWM */
-	dev = PNP_DEV(0x4e, W83627EHG_HWM);
+	dev = W83627EHG_HWM_DEV;
 	pnp_set_logical_device(dev);
 	pnp_set_enable(dev, 0);
 	pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h
index e74dbef..e393750 100644
--- a/src/superio/winbond/w83627ehg/w83627ehg.h
+++ b/src/superio/winbond/w83627ehg/w83627ehg.h
@@ -18,6 +18,8 @@
 #ifndef SUPERIO_WINBOND_W83627EHG_H
 #define SUPERIO_WINBOND_W83627EHG_H
 
+#include <device/pnp_type.h>
+
 #define W83627EHG_FDC              0   /* Floppy */
 #define W83627EHG_PP               1   /* Parallel port */
 #define W83627EHG_SP1              2   /* Com1 */
@@ -50,4 +52,23 @@
 #define W83627EHG_GPIO4	((2 << 8) | W83627EHG_GPIO_SUSLED_V)
 #define W83627EHG_GPIO5	((3 << 8) | W83627EHG_GPIO_SUSLED_V)
 
+#define SUPERIO_DEV		PNP_DEV(CONFIG_SUPERIO_ADDRESS, 0)
+#define W83627EHG_FDC_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_FDC_DEV)
+#define W83627EHG_PP_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_PP_DEV)
+#define W83627EHG_SP1_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_SP1_DEV)
+#define W83627EHG_SP2_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_SP2_DEV)
+#define W83627EHG_KBC_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_KBC_DEV)
+#define W83627EHG_WDTO_PLED_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_WDTO_PLED_DEV)
+#define W83627EHG_ACPI_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_ACPI_DEV)
+#define W83627EHG_HWM_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_HWM_DEV)
+
+#define W83627EHG_GPIO1_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO1_DEV)
+#define W83627EHG_GPIO2_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO2_DEV)
+#define W83627EHG_GPIO3_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO3_DEV)
+#define W83627EHG_GPIO4_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO4_DEV)
+#define W83627EHG_GPIO5_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO5_DEV)
+#define W83627EHG_GPIO6_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GPIO6_DEV)
+#define W83627EHG_GAME_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_GAME_DEV)
+#define W83627EHG_MIDI_DEV	PNP_DEV(CONFIG_SUPERIO_ADDRESS, W83627EHG_MIDI_DEV)
+
 #endif /* SUPERIO_WINBOND_W83627EHG_H */

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