Martin Roth has uploaded this change for review.

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mb/google/guybrush: Reorganize bootblock_mainboard_early_init()

This now skips all of the pieces done by PSP_verstage.

BUG=None
TEST=Boot Guybrush with & without PSP_verstage

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b
---
M src/mainboard/google/guybrush/bootblock.c
1 file changed, 15 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/57318/1

diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c
index dc5e046..cd27632 100644
--- a/src/mainboard/google/guybrush/bootblock.c
+++ b/src/mainboard/google/guybrush/bootblock.c
@@ -31,21 +31,6 @@
 	size_t base_num_gpios, override_num_gpios;
 	const struct soc_amd_gpio *base_gpios, *override_gpios;
 
-	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
-		base_gpios = variant_early_gpio_table(&base_num_gpios);
-		override_gpios = variant_early_override_gpio_table(&override_num_gpios);
-
-		gpio_configure_pads_with_override(base_gpios, base_num_gpios,
-				override_gpios, override_num_gpios);
-
-		/* Set a timer to make sure there's enough delay for
-		 * the Fibocom 350 PCIe init
-		 */
-		stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
-	}
-
-	printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
-
 	dword = pci_read_config32(SOC_LPC_DEV, 0x78);
 	dword &= 0xFFFFF9F3;
 	dword |= 0x200;
@@ -53,6 +38,21 @@
 	pci_write_config32(SOC_LPC_DEV, 0x44, 0);
 	pci_write_config32(SOC_LPC_DEV, 0x48, 0);
 
+	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+		return;
+
+	base_gpios = variant_early_gpio_table(&base_num_gpios);
+	override_gpios = variant_early_override_gpio_table(&override_num_gpios);
+
+	gpio_configure_pads_with_override(base_gpios, base_num_gpios,
+			override_gpios, override_num_gpios);
+
+	/* Set a timer to make sure there's enough delay for
+	 * the Fibocom 350 PCIe init
+	 */
+	stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
+	printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
+
 	dword = pm_read32(0x90);
 	dword |= 1 << 16;
 	pm_write32(0x90, dword);

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