1 comment:
File src/mainboard/kontron/mal10/romstage.c:
mupd->FspmConfig.Ch0_RankEnable = 0;
mupd->FspmConfig.Ch0_DeviceWidth = 0;
mupd->FspmConfig.Ch0_DramDensity = 0;
mupd->FspmConfig.Ch0_Option = 0;
mupd->FspmConfig.Ch1_RankEnable = 0;
mupd->FspmConfig.Ch1_DeviceWidth = 0;
mupd->FspmConfig.Ch1_DramDensity = 0;
mupd->FspmConfig.Ch1_Option = 0;
mupd->FspmConfig.Ch2_RankEnable = 0;
mupd->FspmConfig.Ch2_DeviceWidth = 0;
mupd->FspmConfig.Ch2_DramDensity = 0;
mupd->FspmConfig.Ch2_Option = 0;
mupd->FspmConfig.Ch3_RankEnable = 0;
mupd->FspmConfig.Ch3_DeviceWidth = 0;
mupd->FspmConfig.Ch3_DramDensity = 0;
mupd->FspmConfig.Ch3_Option = 0;
Huh?
I think it would be better if I remove this, because the options DIMM0SPDAddress and DIMM1SPDAddress (same as for apl_rvp1 https://github.com/coreboot/coreboot/blob/ef7a3267870f126cc2f815812cfe54500853d2b8/src/mainboard/intel/apollolake_rvp/romstage.c#L51) tell us that the memory controller uses the settings from SPD. I think that this will be enough.
To view, visit change 39133. To unsubscribe, or for help writing mail filters, visit settings.