[coreboot-gerrit] Change in coreboot[master]: mainboard/google/kahlee: Enable elog in Kconfig

[John E. Kabat Jr. (Code Review)]

John E. Kabat Jr. has uploaded this change for review. ( https://review.coreboot.org/22636

Change subject: mainboard/google/kahlee: Enable elog in Kconfig
......................................................................

mainboard/google/kahlee: Enable elog in Kconfig

- Change kahlee/Kconfig to enable elog and save the boot count in cmos.
- Change soc/amd/common/Makefile to not include common/spi.c unless S3
is enabled.
- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES

BUG=b:65485690
TEST=Build & boot kahlee.
     WIP - More testing to follow with boot to ChromeOS.

Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Signed-off-by: John E. Kabat Jr 
---
M src/mainboard/google/kahlee/Kconfig
M src/soc/amd/common/Makefile.inc
M src/soc/amd/stoneyridge/Kconfig
3 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22636/1

diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig
index 6c9bfcc..f075a9f 100644
--- a/src/mainboard/google/kahlee/Kconfig
+++ b/src/mainboard/google/kahlee/Kconfig
@@ -29,6 +29,10 @@
    select MAINBOARD_HAS_LPC_TPM
    select SERIRQ_CONTINUOUS_MODE
    select STONEYRIDGE_UART
+	select ELOG
+	select ELOG_GSMI
+	select ELOG_BOOT_COUNT
+

if BOARD_GOOGLE_BASEBOARD_KAHLEE

@@ -97,4 +101,12 @@
    int
    default 1

+config ELOG_BOOT_COUNT_CMOS_OFFSET
+	depends on ELOG && ELOG_BOOT_COUNT && !USE_OPTION_TABLE
+	int "Offset in CMOS to store the boot count"
+	default 144
+	help
+	  This value must be greater than 16 bytes so as not to interfere
+	  with the standard RTC region.  Requires 8 bytes.
+
 endif # BOARD_GOOGLE_KAHLEE || BOARD_GOOGLE_GRUNT
diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc
index aa27512..7ccb1c2 100644
--- a/src/soc/amd/common/Makefile.inc
+++ b/src/soc/amd/common/Makefile.inc
@@ -15,8 +15,9 @@
 ramstage-y += amd_pci_util.c
 ramstage-y += def_callouts.c
 ramstage-y += heapmanager.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
-
+ifeq ($(CONFIG_SPI_FLASH),y)
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
+endif
 subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block

endif
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 7f44883..fa8d842 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -50,6 +50,7 @@
    select SOC_AMD_COMMON_BLOCK_CAR
    select C_ENVIRONMENT_BOOTBLOCK
    select BOOTBLOCK_CONSOLE
+	select BOOT_DEVICE_SUPPORTS_WRITES
    select RELOCATABLE_MODULES
    select PARALLEL_MP
    select HAVE_SMI_HANDLER