Attention is currently required from: Jason Glenesk, Marshall Dawson, Eric Peers, Yu-hsuan Hsu, Karthik Ramasubramanian, Felix Held.

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5 comments:

• Commit Message:

  • Patch Set #1, Line 7: [WIP]: soc/amd/cezanne: Generate PCI routing table

    Yeah, we still have outstanding questions.

    Done

• Patchset:

  • Patch Set #2:

    PTAL

• File src/soc/amd/cezanne/pcie_gpp.c:

  • Patch Set #1, Line 59:

    tatic const struct pci_logical_map pci_logical_numbers[] = {
    	{PCIE_GPP_1_0_DEVFN, 1},
    	{PCIE_GPP_1_1_DEVFN, 5},
    	{PCIE_GPP_1_2_DEVFN, 6},
    
    	{PCIE_GPP_2_0_DEVFN, 7},
    	{PCIE_GPP_2_1_DEVFN, 8},
    	{PCIE_GPP_2_2_DEVFN, 3},
    	{PCIE_GPP_2_3_DEVFN, 4},
    	{PCIE_GPP_2_4_DEVFN, 0},
    	{PCIE_GPP_2_5_DEVFN, 2},
    	{PCIE_GPP_2_6_DEVFN, 9},
    
    	{PCIE_ABC_A_DEVFN,   10},
    	{PCIE_GPP_B_DEVFN,   11},
    	{PCIE_GPP_C_DEVFN,   12},
    };
    

    It looks like you are right. We might need to pull this out into mainboard.c. […]

    Done

  • Patch Set #1, Line 88: PPR 55570

    Requires fixing - 56569

    Done

  • Patch Set #1, Line 355:

    Yeah, the picasso version of this file contains that.

    Done

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