Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel.
Hello Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/77556?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs ......................................................................
drivers/intel/fsp2_0: Introduce MRC cache store after FSP-M/S APIs
This patch refactors the existing MRC cache storing logic, which was spread between the ROM and RAM stages, into a single early MRC cache store stage. The only exception is when SoC user selects FSP_NVS_DATA_POST_SILICON_INIT to store MRC cache from ramstage (after FSP-S).
It reverts all the boot-state logic previously used to locate and store MRC cache from NVS HOB into NVS because majority of the platform can potentially use the early MRC cache store with improved memory caching at the pre-RAM phase (with the ramtop implementation).
The only exception is xeon_sp platform (so far) that locates MRC cache post in FSP-S (at ramstage). Hence, this patch provides an API to in FSP 2.x silicon init code to perform late storing of MRC cache.
In majority cases the updated logic, the romstage (post FSP-M) will attempt to save the MRC cache. Platform that selects FSP_NVS_DATA_POST_SILICON_INIT config performs the same operation post FSP-S. Depending on whether the MRC_STASH_TO_CBMEM config is enabled, the MRC cache will either be written directly to NVRAM at the romstage or stashed into CBMEM for a late NVRAM write at ramstage.
Below table captures the change in the boot state w/ and w/o this patch for storing the MRC cache. Overall the goal is to ensure the platform behavior is remain unchanged before and after this patch.
w/o this patch:
| | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | BS_DEV_INIT | BS_DEV | BS_DEV | | DATA_POST | CHIPS_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | BS_PRE | BS_DEV | BS_DEV | | w/o above | DEVICE_ENTRY | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | |
w/ this patch:
| | Save MRC | Finalize | Lock the | | | Cache | MRC Cache | Boot Medium | +-----------+----------------+----------------+----------------+ | MRC_WRITE | BS_OS_RESUME | BS_OS_RESUME | BS_ON_RESUME | | NV_LATE | CHECK_ENTRY | CHECK_ENTRY | CHECK_EXIT | +-----------+----------------+----------------+----------------+ | MRC_STASH | BS_DEV | BS_DEV | BS_DEV | | TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY| +-----------+----------------+----------------+----------------+ | FSP_NVS | Post FSP-S | BS_DEV | BS_DEV | | DATA_POST | (ramstage) | ENUMERATE_EXIT | RESOURCES_ENTRY| | SILICON | | | | | INIT | | | | +-----------+----------------+----------------+----------------+ | Platform | Post FSP-M | BS_DEV | BS_DEV | | w/o above | (romstage) | ENUMERATE_EXIT | ENUMERATE_ENTRY| | config | | | | | (FSP 2.0 | | | | | platforms | | | |
BUG=b:296704537 TEST=Able to build and boot google/rex without any boot time impact.
Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Signed-off-by: Subrata Banik subratabanik@google.com --- M src/drivers/intel/fsp2_0/Makefile.inc M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/save_mrc_data.c M src/drivers/intel/fsp2_0/silicon_init.c M src/include/mrc_cache.h 5 files changed, 17 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/77556/6