Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/29551 )
Change subject: mb/cannonlake: Remove SmbusEnable from devicetree ......................................................................
mb/cannonlake: Remove SmbusEnable from devicetree
Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device.
Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/29551 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/zoombini/variants/baseboard/devicetree.cb M src/mainboard/google/zoombini/variants/meowth/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb 7 files changed, 0 insertions(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index c7ef264..36c6595 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@
# FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
# Intel Common SoC Config diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index c3a546e..b014353 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,6 @@
# FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
# Intel Common SoC Config diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index da439d5..bb963c9 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -6,7 +6,6 @@
# FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index a1c8586..55afde2 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -6,7 +6,6 @@
# FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 4a2fad9..35aa624 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -7,7 +7,6 @@ # FSP configuration register "SaGv" = "3" register "RMT" = "1" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 2b47f00..bbfc9e7 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -7,7 +7,6 @@ # FSP configuration register "SaGv" = "3" register "RMT" = "1" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb index da439d5..bb963c9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/devicetree.cb @@ -6,7 +6,6 @@
# FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"