Subrata Banik submitted this change.

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1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.

Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified
soc/intel/elkhartlake: Switch to common eSPI header

This patch updates Elkhart Lake code to use the common eSPI header
file(`intelpch/espi.h`) instead of the SoC-specific one.

BUG=none
TEST=Builds successfully for Intel Elkhartlake platform.

Change-Id: Iaef308ad1c8ecfb11448e75f39285a2170bbc49c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83485
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/elkhartlake/bootblock/pch.c
M src/soc/intel/elkhartlake/espi.c
D src/soc/intel/elkhartlake/include/soc/espi.h
M src/soc/intel/elkhartlake/pmutil.c
4 files changed, 3 insertions(+), 31 deletions(-)

diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c
index 9541c4b..a634b2b 100644
--- a/src/soc/intel/elkhartlake/bootblock/pch.c
+++ b/src/soc/intel/elkhartlake/bootblock/pch.c
@@ -12,8 +12,8 @@
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
+#include <intelpch/espi.h>
#include <soc/bootblock.h>
-#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/p2sb.h>
#include <soc/pch.h>
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c
index 3c9e81b..15bf932 100644
--- a/src/soc/intel/elkhartlake/espi.c
+++ b/src/soc/intel/elkhartlake/espi.c
@@ -6,9 +6,9 @@
#include <device/pci_ops.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
+#include <intelpch/espi.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
-#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/elkhartlake/include/soc/espi.h b/src/soc/intel/elkhartlake/include/soc/espi.h
deleted file mode 100644
index 65ee732..0000000
--- a/src/soc/intel/elkhartlake/include/soc/espi.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_ELKHARTLAKE_ESPI_H_
-#define _SOC_ELKHARTLAKE_ESPI_H_
-
-
-/* PCI Configuration Space (D31:F0): ESPI */
-#define SCI_IRQ_SEL (7 << 0)
-#define SCIS_IRQ9 0
-#define SCIS_IRQ10 1
-#define SCIS_IRQ11 2
-#define SCIS_IRQ20 4
-#define SCIS_IRQ21 5
-#define SCIS_IRQ22 6
-#define SCIS_IRQ23 7
-#define SERIRQ_CNTL 0x64
-#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */
-#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
-#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
-#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */
-#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */
-#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
-#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
-#define LGMR 0x98 /* ESPI Generic Memory Range */
-#define PCCTL 0xE0 /* PCI Clock Control */
-#define CLKRUN_EN (1 << 0)
-
-#endif
diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c
index adc3056..c9ae847 100644
--- a/src/soc/intel/elkhartlake/pmutil.c
+++ b/src/soc/intel/elkhartlake/pmutil.c
@@ -16,8 +16,8 @@
#include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h>
#include <intelblocks/tco.h>
+#include <intelpch/espi.h>
#include <security/vboot/vbnv.h>
-#include <soc/espi.h>
#include <soc/gpe.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>

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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iaef308ad1c8ecfb11448e75f39285a2170bbc49c
Gerrit-Change-Number: 83485
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subratabanik@google.com>
Gerrit-Reviewer: Eric Lai <ericllai@google.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan@9elements.com>
Gerrit-Reviewer: Subrata Banik <subratabanik@google.com>
Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>