Attention is currently required from: Saurabh Mishra.
Saurabh Mishra would like Saurabh Mishra to review this change.
vc/intel/fsp:Update JSL FSP headers from v2385.04 to v4155.00
The headers added are generated as per FSP v4155.00.
Previous FSP version was v2385.04
Changes Include:
FspsUpd.h: Change in header offset.
{FspmUpd.h,FspUpd.h & FirmwareVersionInfo.h}: Copyright year update.
MemInfoHob.h: Add HOB_GUID_TYPE, HOB_GENERIC_HEADER Struct.
BUG=b:TBD
BRANCH=firmware-dedede-13606.B
TEST=Build and boot JSLRVP
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: Ic4fae89d8d7fbbcb0448222d39dd829bc3f99644
---
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h
5 files changed, 338 insertions(+), 281 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/69107/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h
index e855038..9f04b3b 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FirmwareVersionInfo.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h
index b28ba78..37ce01f 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
index 55f8418..350e3db 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -2286,7 +2286,7 @@
/** Offset 0x0567 - Row Hammer Solution
Type of method used to prevent Row Hammer. Default is 2x Refresh
- 0:Hardware RHP, 1:2x Refresh
+ 0:Hardware RHP, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh, 4:NORMAL Refresh
**/
UINT8 RhSolution;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
index c12345f..4872212 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -875,8 +875,10 @@
UINT8 PavpEnable;
/** Offset 0x0436 - CdClock Frequency selection
- 0: 172.8 MHz, 1: 180 MHz, 2: 192 MHz, 3: 307 MHz, 4: 312 MHz, 5: 552 MHz, 6: 556.8 MHz,
- 0xff: 556.8 MHz (Default)
+ 0xFF: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2:
+ 180 Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz
+ 0xFF: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3:
+ 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz
**/
UINT8 CdClock;
@@ -2912,7 +2914,7 @@
/** Offset 0x0C8D - Reserved
**/
- UINT8 Reserved43[83];
+ UINT8 Reserved43[91];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -2931,11 +2933,11 @@
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x0CE0
+/** Offset 0x0CE8
**/
UINT8 UnusedUpdSpace35[6];
-/** Offset 0x0CE6
+/** Offset 0x0CEE
**/
UINT16 UpdTerminator;
} FSPS_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h
index 35cdd2a..f9bc878 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/jasperlake/MemInfoHob.h
@@ -1,271 +1,305 @@
-/** @file
- This file contains definitions required for creation of
- Memory S3 Save data, Memory Info data and Memory Platform
- data hobs.
-
- @copyright
- Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License that accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-@par Specification Reference:
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#pragma pack (push, 1)
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_TRACE_CACHE_TYPE 3
-
-#define MAX_NODE 1
-#define MAX_CH 2
-#define MAX_DIMM 2
-
-///
-/// Host reset states from MRC.
-///
-#define WARM_BOOT 2
-
-#define R_MC_CHNL_RANK_PRESENT 0x7C
-#define B_RANK0_PRS BIT0
-#define B_RANK1_PRS BIT1
-#define B_RANK2_PRS BIT4
-#define B_RANK3_PRS BIT5
-
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
- UINT8 Major; ///< Major version number
- UINT8 Minor; ///< Minor version number
- UINT8 Rev; ///< Revision number
- UINT8 Build; ///< Build number
-} SiMrcVersion;
-
-//// Matches MrcChannelSts enum in MRC
-//
-#ifndef CHANNEL_NOT_PRESENT
-#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
-#endif
-#ifndef CHANNEL_DISABLED
-#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
-#endif
-#ifndef CHANNEL_PRESENT
-#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
-#endif
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef __MRC_BOOT_MODE__
-#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
- #ifndef INT32_MAX
- #define INT32_MAX (0x7FFFFFFF)
- #endif //INT32_MAX
-typedef enum {
- bmCold, ///< Cold boot
- bmWarm, ///< Warm boot
- bmS3, ///< S3 resume
- bmFast, ///< Fast boot
- MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
- MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
-} MRC_BOOT_MODE;
-#endif //__MRC_BOOT_MODE__
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR4
-#define MRC_DDR_TYPE_LPDDR4 3
-#endif
-#ifndef MRC_DDR_TYPE_WIO2
-#define MRC_DDR_TYPE_WIO2 4
-#endif
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 5
-#endif
-
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
- UINT32 tCK; ///< Memory cycle time, in femtoseconds.
- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
- UINT16 Speed; ///< The maximum capable speed of the device, in MHz
- UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
-} CONTROLLER_INFO;
-
-typedef struct {
- UINT64 BaseAddress; ///< Trace Base Address
- UINT64 TotalSize; ///< Total Trace Region of Same Cache type
- UINT8 CacheType; ///< Trace Cache Type
- UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
- UINT8 Rsvd[2];
-} PSMI_MEM_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT16 DataWidth; ///< Data width, in bits, of this memory device
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
-
- SiMrcVersion Version;
- BOOLEAN EccSupport;
- UINT8 MemoryProfile;
- UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
- UINT8 Ratio;
- UINT8 RefClk;
- UINT32 VddVoltage[MAX_PROFILE_NUM];
- CONTROLLER_INFO Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
- Memory Platform Data Hob
-
- <b>Revision 1:</b>
- - Initial version.
- <b>Revision 2:</b>
- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 BootMode;
- UINT32 TsegSize;
- UINT32 TsegBase;
- UINT32 PrmrrSize;
- UINT64 PrmrrBase;
- UINT32 PramSize;
- UINT64 PramBase;
- UINT64 DismLimit;
- UINT64 DismBase;
- UINT32 GttBase;
- UINT32 MmioSize;
- UINT32 PciEBaseAddress;
- PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
- MEMORY_PLATFORM_DATA Data;
- UINT8 *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
+/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
+
+@copyright
+ INTEL CONFIDENTIAL
+ Copyright 1999 - 2020 Intel Corporation.
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
+
+@par Specification Reference:
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_TRACE_CACHE_TYPE 3
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
+#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
+#ifndef __HOB__H__
+typedef struct _EFI_HOB_GENERIC_HEADER {
+ UINT16 HobType;
+ UINT16 HobLength;
+ UINT32 Reserved;
+} EFI_HOB_GENERIC_HEADER;
+
+typedef struct _EFI_HOB_GUID_TYPE {
+ EFI_HOB_GENERIC_HEADER Header;
+ EFI_GUID Name;
+ ///
+ /// Guid specific data goes here
+ ///
+} EFI_HOB_GUID_TYPE;
+#endif
+#endif
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcChannelSts enum in MRC
+//
+#ifndef CHANNEL_NOT_PRESENT
+#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
+#endif
+#ifndef CHANNEL_DISABLED
+#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
+#endif
+#ifndef CHANNEL_PRESENT
+#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
+#endif
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef __MRC_BOOT_MODE__
+#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
+ #ifndef INT32_MAX
+ #define INT32_MAX (0x7FFFFFFF)
+ #endif //INT32_MAX
+typedef enum {
+ bmCold, ///< Cold boot
+ bmWarm, ///< Warm boot
+ bmS3, ///< S3 resume
+ bmFast, ///< Fast boot
+ MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
+ MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
+} MRC_BOOT_MODE;
+#endif //__MRC_BOOT_MODE__
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR4
+#define MRC_DDR_TYPE_LPDDR4 3
+#endif
+#ifndef MRC_DDR_TYPE_WIO2
+#define MRC_DDR_TYPE_WIO2 4
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 5
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT64 BaseAddress; ///< Trace Base Address
+ UINT64 TotalSize; ///< Total Trace Region of Same Cache type
+ UINT8 CacheType; ///< Trace Cache Type
+ UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
+ UINT8 Rsvd[2];
+} PSMI_MEM_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+/**
+ Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
+**/
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT64 PrmrrBase;
+ UINT32 PramSize;
+ UINT64 PramBase;
+ UINT64 DismLimit;
+ UINT64 DismBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+ PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
+} MEMORY_PLATFORM_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType;
+ MEMORY_PLATFORM_DATA Data;
+ UINT8 *Buffer;
+} MEMORY_PLATFORM_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
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