Brandon Breitenstein would like Divya S Sasidharan to review this change.
src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
EC being the TCPM decides the mux configuration after
negotiating with the port partner on the Type-C port. The APIS
added here will give the current essential mux state information
for a given port.
BUG=None
BRANCH=None
TEST= Tested boots from USB Type-C flash drive and Type-C to
Type-A dongle on Volteer
Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec.h
M src/ec/google/chromeec/ec_commands.h
3 files changed, 105 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42078/1
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index a97dfb3..22e57d2 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -1374,7 +1374,7 @@
return ec_image_type;
}
-int google_chromeec_get_num_pd_ports(int *num_ports)
+int google_chromeec_get_num_pd_ports(uint8_t *num_ports)
{
struct ec_response_charge_port_count resp = {};
struct chromeec_command cmd = {
@@ -1435,6 +1435,91 @@
return (google_chromeec_get_current_image() == EC_IMAGE_RO);
}
+int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode)
+{
+ struct ec_params_usb_pd_control pd_control = {
+ .port = port,
+ .role = USB_PD_CTRL_ROLE_NO_CHANGE,
+ .mux = USB_PD_CTRL_ROLE_NO_CHANGE,
+ .swap = USB_PD_CTRL_SWAP_NONE,
+ };
+ struct ec_response_usb_pd_control_v2 resp = {};
+ struct chromeec_command cmd = {
+ .cmd_code = EC_CMD_USB_PD_CONTROL,
+ .cmd_version = 2,
+ .cmd_data_in = &pd_control,
+ .cmd_size_in = sizeof(pd_control),
+ .cmd_data_out = &resp,
+ .cmd_size_out = sizeof(resp),
+ .cmd_dev_index = 0,
+ };
+
+ if (google_chromeec_command(&cmd) < 0)
+ return -1;
+
+ *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED);
+ *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC);
+ *dp_mode = resp.dp_mode;
+
+ return 0;
+}
+
+/**
+ * Return USB2 port mapping in bit 0:3
+ * USB3 port mapping in bit 4:7
+ */
+int google_chromeec_pd_get_port_info(int port, uint8_t *port_map)
+{
+ struct ec_params_locate_chip req = {
+ .type = EC_CHIP_TYPE_TCPC,
+ .index = port,
+ };
+ struct ec_response_locate_chip resp = {};
+ struct chromeec_command cmd = {
+ .cmd_code = EC_CMD_LOCATE_CHIP,
+ .cmd_version = 0,
+ .cmd_data_in = &req,
+ .cmd_size_in = sizeof(req),
+ .cmd_data_out = &resp,
+ .cmd_size_out = sizeof(resp),
+ };
+
+ if (google_chromeec_command(&cmd) < 0)
+ return -1;
+
+ *port_map = resp.reserved;
+ return 0;
+}
+
+/**
+ * Check for the current mux state in EC
+ * Flags representing mux state can be
+ * found in ec_commands.h
+ */
+int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags)
+{
+ if (port < 0)
+ return -1;
+ struct ec_params_usb_pd_mux_info req_mux = {
+ .port = port,
+ };
+ struct ec_response_usb_pd_mux_info resp_mux = {};
+ struct chromeec_command cmd = {
+ .cmd_code = EC_CMD_USB_PD_MUX_INFO,
+ .cmd_version = 0,
+ .cmd_data_in = &req_mux,
+ .cmd_size_in = sizeof(req_mux),
+ .cmd_data_out = &resp_mux,
+ .cmd_size_out = sizeof(resp_mux),
+ .cmd_dev_index = 0,
+ };
+ if (google_chromeec_command(&cmd) < 0)
+ return -1;
+
+ *flags = resp_mux.flags;
+ return 0;
+}
+
/**
* Check if EC/TCPM is in an alternate mode or not.
*
@@ -1443,22 +1528,16 @@
*/
int google_chromeec_pd_get_amode(uint16_t svid)
{
- struct ec_response_usb_pd_ports resp;
- struct chromeec_command cmd = {
- .cmd_code = EC_CMD_USB_PD_PORTS,
- .cmd_version = 0,
- .cmd_data_in = NULL,
- .cmd_size_in = 0,
- .cmd_data_out = &resp,
- .cmd_size_out = sizeof(resp),
- .cmd_dev_index = 0,
- };
+ uint8_t num_ports;
+ int ret;
+ struct chromeec_command cmd;
int i;
- if (google_chromeec_command(&cmd) < 0)
+ ret = google_chromeec_get_num_pd_ports(&num_ports);
+ if (ret < 0)
return -1;
- for (i = 0; i < resp.num_ports; i++) {
+ for (i = 0; i < num_ports; i++) {
struct ec_params_usb_pd_get_mode_request params;
struct ec_params_usb_pd_get_mode_response resp2;
int svid_idx = 0;
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index aead5f7..3d95c16 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -27,6 +27,17 @@
enum ec_image google_chromeec_get_current_image(void);
void google_chromeec_init(void);
int google_chromeec_pd_get_amode(uint16_t svid);
+/* Check for the current mux state in EC */
+int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags);
+/*
+ * USB2 and USB3 port numbers between EC and AP
+ * is not one to one mapping, this function will return the
+ * correct mapped AP port number in port_map.
+ */
+int google_chromeec_pd_get_port_info(int port, uint8_t *port_map);
+/* Returns data role and type of device connected */
+int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc,
+ uint8_t *dp_mode);
int google_chromeec_wait_for_displayport(long timeout);
/* Device events */
@@ -306,7 +317,7 @@
* of PD-capable USB ports according to the EC.
* @return 0 on success, -1 on error
*/
-int google_chromeec_get_num_pd_ports(int *num_ports);
+int google_chromeec_get_num_pd_ports(uint8_t *num_ports);
/* Structure representing the capabilities of a USB-PD port */
struct usb_pd_port_caps {
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 62761a2..b4a8ee1 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -5331,10 +5331,6 @@
/* Active Link Uni-Direction */
#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
-/*
- * Underdevelopement :
- * Please remove this tag if using _v2 outside platform/ec
- */
struct ec_response_usb_pd_control_v2 {
uint8_t enabled;
uint8_t role;
@@ -5641,7 +5637,7 @@
#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
struct ec_response_usb_pd_mux_info {
- uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
+ uint8_t flags; /* USB_PD_CTRL_*-encoded USB mux state */
} __ec_align1;
#define EC_CMD_PD_CHIP_INFO 0x011B
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