Johnny Lin has uploaded this change for review.
soc/intel/xeon_sp/cpx: Configure serverl power-related MSRs
Configure MSR_PKG_CST_CONFIG_CONTROL, MSR_PMG_IO_CAPTURE_BASE,
MSR_POWER_CTL, MSR_IA32_PERF_CTRL, MSR_VR_CURRENT_CONFIG and
MSR_TURBO_ACTIVATION_RATIO.
Tested=On OCP Delta Lake, rdmsr to check the results are expected.
Change-Id: I5112629acf06e66d92d944fd3f698e34f4b5e5aa
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
---
M src/soc/intel/xeon_sp/cpx/cpu.c
1 file changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45332/1
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c
index 6737bf0..5942120 100644
--- a/src/soc/intel/xeon_sp/cpx/cpu.c
+++ b/src/soc/intel/xeon_sp/cpx/cpu.c
@@ -63,7 +63,27 @@
printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n",
__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
setup_lapic();
+ /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/
+ msr.hi = 0;
+ msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE);
+ wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
+ /* set MSR_PMG_IO_CAPTURE_BASE - scope per core */
+ msr.hi = 0;
+ msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6);
+ wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
+ /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */
+ msr = rdmsr(MSR_POWER_CTL);
+ msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE
+ | PROCHOT_LOCK_ENABLE);
+ wrmsr(MSR_POWER_CTL, msr);
+
+ /* Set P-State ratio */
+ msr = rdmsr(MSR_IA32_PERF_CTRL);
+ msr.lo &= ~PSTATE_REQ_MASK;
+ msr.lo |= (chip_config->pstate_req_ratio << PSTATE_REQ_SHIFT);
+ wrmsr(MSR_IA32_PERF_CTRL, msr);
/*
* Set HWP base feature, EPP reg enumeration, lock thermal and msr
* This is package level MSR. Need to check if it updates correctly on
@@ -76,10 +96,24 @@
wrmsr(MSR_MISC_PWR_MGMT, msr);
}
+ /* TODO MSR_VR_MISC_CONFIG */
+
+ /* Set current limit lock */
+ msr = rdmsr(MSR_VR_CURRENT_CONFIG);
+ msr.lo |= CURRENT_LIMIT_LOCK;
+ wrmsr(MSR_VR_CURRENT_CONFIG, msr);
+
+ /* set Turbo Activation ratio */
+ msr.hi = 0;
+ msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
+ msr.lo |= MAX_NON_TURBO_RATIO;
+ wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
+
/* Enable Fast Strings */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= FAST_STRINGS_ENABLE_BIT;
wrmsr(IA32_MISC_ENABLE, msr);
+
/* Enable Turbo */
enable_turbo();
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