[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add chip configuration for I2C devices

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72647 )

Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices
......................................................................

mb/intel/mtlrvp: Add chip configuration for I2C devices

This patch adds below chip configuration for I2C devices for mtlrvp.

+-----------+--------------------+-------------+
| INTERFACE | PCI Number (B:D:F) | DEVICE      |
+-----------+--------------------+-------------+
|   I2C0    | 0:0x15:0           | CAM1        |
+-----------+--------------------+-------------+
|   I2C1    | 0:0x15:1           | CAM0        |
+-----------+--------------------+-------------+
|   I2C2    | 0:0x15:2           | NC          |
+-----------+--------------------+-------------+
|   I2C3    | 0:0x15:3           | HID         |
+-----------+--------------------+-------------+
|   I2C4    | 0:0x15:4           | NC          |
+-----------+--------------------+-------------+
|   I2C5    | 0:0x15:5           | NC          |
+-----------+--------------------+-------------+

BUG=b:224325352
BRANCH=None
TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus
enumeration through lspci.

00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01)
00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01)
00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01)

Signed-off-by: Harsha B R 
Change-Id: Ia5964472be902041f961187c0072a89055badd4f
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Sridhar Siricilla 
---
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
1 file changed, 65 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sridhar Siricilla: Looks good to me, approved
  Eric Lai: Looks good to me, approved

diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 27d153f..628a8cb 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -46,6 +46,29 @@
    	[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
    }"

+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+	}"
+
+	# Intel Common SoC Config
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
    device domain 0 on
    	device ref igpu on end
    	device ref heci1 on end