Arthur Heymans has uploaded this change for review.
nb/intel/nehalem: Introduce macros to reduce indentation level
While the indentation of the code is adapted to the new macro's the
wrapping is not fixed. A followup commit running this code through
clang-format will do that.
TEST: build with BUILD_TIMELESS=1, hash of resulting binary is
identical before and after.
Change-Id: I95358d49b57e771d86a562702403f491a02fe017
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/northbridge/intel/nehalem/raminit.c
1 file changed, 527 insertions(+), 491 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/36083/1
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index b9d407a..dde51f9 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -50,22 +50,57 @@
#define HECIDEV PCI_DEV(0, 0x16, 0)
#define HECIBAR 0x10
-#define FOR_ALL_RANKS \
- for (channel = 0; channel < NUM_CHANNELS; channel++) \
- for (slot = 0; slot < NUM_SLOTS; slot++) \
- for (rank = 0; rank < NUM_RANKS; rank++)
+#define RANK_IS_POPULATED(info, channel, slot, rank) \
+ ((info)->populated_ranks[(channel)][(slot)][(rank)] != 0)
-#define FOR_POPULATED_RANKS \
- for (channel = 0; channel < NUM_CHANNELS; channel++) \
- for (slot = 0; slot < NUM_SLOTS; slot++) \
- for (rank = 0; rank < NUM_RANKS; rank++) \
- if (info->populated_ranks[channel][slot][rank])
+#define IF_RANK_POPULATED(info, channel, slot, rank) \
+ if (RANK_IS_POPULATED(info, channel, slot, rank))
-#define FOR_POPULATED_RANKS_BACKWARDS \
- for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) \
- for (slot = 0; slot < NUM_SLOTS; slot++) \
- for (rank = 0; rank < NUM_RANKS; rank++) \
- if (info->populated_ranks[channel][slot][rank])
+#define FOR_EACH_CHANNEL(channel) \
+ for (channel = 0; channel < NUM_CHANNELS; channel++)
+
+#define FOR_EACH_SLOT(slot) \
+ for (slot = 0; slot < NUM_SLOTS; slot++)
+
+#define FOR_ALL_SLOTS(channel, slot) \
+ FOR_EACH_CHANNEL(channel) \
+ FOR_EACH_SLOT(slot)
+
+#define FOR_ALL_POPULATED_SLOTS(info, channel, slot) \
+ FOR_ALL_SLOTS(channel, slot) \
+ IF_RANK_POPULATED(info, channel, slot, 0)
+
+#define FOR_EACH_RANK(rank) \
+ for (rank = 0; rank < NUM_RANKS; rank++)
+
+#define FOR_ALL_RANKS(channel, slot, rank) \
+ FOR_ALL_SLOTS(channel, slot) \
+ FOR_EACH_RANK(rank)
+
+#define FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
+ FOR_EACH_SLOT(slot) \
+ FOR_EACH_RANK(rank)
+
+#define FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) \
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) \
+ IF_RANK_POPULATED(info, channel, slot, rank)
+
+#define FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) \
+ FOR_ALL_RANKS(channel, slot, rank) \
+ IF_RANK_POPULATED(info, channel, slot, rank)
+
+#define FOR_EACH_CHANNEL_BACKWARDS(channel) \
+ for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)
+
+#define FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) \
+ FOR_EACH_CHANNEL_BACKWARDS(channel) \
+ FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank)
+
+#define FOR_EACH_LANE(lane) \
+ for (lane = 0; lane < 8; lane++)
+
+#define FOR_EACH_LANE_WITH_ECC(lane) \
+ for (lane = 0; lane < 9; lane++)
/* [REG_178][CHANNEL][2 * SLOT + RANK][LANE] */
typedef struct {
@@ -315,7 +350,7 @@
program_timings(struct raminfo *info, u16 base, int channel, int slot, int rank)
{
int lane;
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
base +
info->training.
@@ -363,7 +398,7 @@
int i, lane;
for (i = 0; i < 2; i++)
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
info->training.lane_timings[i +
1][channel][slot]
@@ -372,24 +407,22 @@
slot,
rank),
9, 0);
+ }
write_1d0(1, 0x103, 6, 1);
- for (lane = 0; lane < 8; lane++)
- write_500(info, channel,
- info->training.
- lane_timings[0][channel][slot][rank][lane],
+ FOR_EACH_LANE(lane) {
+ write_500(info, channel, info->training.lane_timings[0][channel][slot]
+ [rank][lane],
get_timing_register_addr(lane, 0, slot, rank), 9, 0);
+ }
for (i = 0; i < 2; i++) {
- for (lane = 0; lane < 8; lane++)
- write_500(info, channel,
- info->training.lane_timings[i +
- 1][channel][slot]
- [rank][lane], get_timing_register_addr(lane,
- i + 1,
- slot,
- rank),
+ FOR_EACH_LANE(lane) {
+ write_500(info, channel, info->training.lane_timings[i + 1][channel]
+ [slot] [rank][lane],
+ get_timing_register_addr(lane, i + 1, slot, rank),
9, 0);
+ }
gav(get_580(channel, ((i + 1) << 2) | (rank << 5)));
}
@@ -397,7 +430,7 @@
MCHBAR8(0x5ff) = 0x0;
MCHBAR8(0x5ff) = 0x80;
write_1d0(0x2, 0x142, 3, 1);
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
// printk (BIOS_ERR, "before: %x\n", info->training.lane_timings[2][channel][slot][rank][lane]);
info->training.lane_timings[2][channel][slot][rank][lane] =
read_500(info, channel,
@@ -413,9 +446,10 @@
{
int slot, rank;
int res = 0;
- for (slot = 0; slot < NUM_SLOTS; slot++)
+ FOR_EACH_SLOT(slot) {
for (rank = 0; rank < NUM_SLOTS; rank++)
res += info->populated_ranks[channel][slot][rank];
+ }
return res;
}
@@ -465,7 +499,7 @@
const u32 val3[] = { 0x2a2b2a2b, 0x26272627, 0x2e2f2e2f, 0x2a2b };
u32 vd8[2][16];
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
for (j = 0; j < 4; j++) {
u32 a = (j == 1) ? 0x29292929 : 0x31313131;
u32 lmask = (j == 3) ? 0xffff : 0xffffffff;
@@ -559,41 +593,25 @@
/* Find common CAS latency */
supported_cas_latencies = 0x3fe;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- if (info->populated_ranks[channel][slot][0])
- supported_cas_latencies &=
- 2 *
- (info->
- spd[channel][slot][CAS_LATENCIES_LSB] |
- (info->
- spd[channel][slot][CAS_LATENCIES_MSB] <<
- 8));
+ FOR_ALL_POPULATED_SLOTS(info, channel, slot) {
+ supported_cas_latencies &= 2 * (info->spd[channel][slot][CAS_LATENCIES_LSB]
+ | (info->spd[channel][slot][CAS_LATENCIES_MSB]
+ << 8));
+ }
max_clock_index = min(3, info->max_supported_clock_speed_index);
cycletime = min_cycletime[max_clock_index];
cas_latency_time = min_cas_latency_time[max_clock_index];
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- if (info->populated_ranks[channel][slot][0]) {
- unsigned timebase;
- timebase =
- 1000 *
- info->
- spd[channel][slot][TIMEBASE_DIVIDEND] /
- info->spd[channel][slot][TIMEBASE_DIVISOR];
- cycletime =
- max(cycletime,
- timebase *
- info->spd[channel][slot][CYCLETIME]);
- cas_latency_time =
- max(cas_latency_time,
- timebase *
- info->
- spd[channel][slot][CAS_LATENCY_TIME]);
- }
+ FOR_ALL_POPULATED_SLOTS(info, channel, slot) {
+ unsigned timebase;
+ timebase = 1000 * info->spd[channel][slot][TIMEBASE_DIVIDEND] /
+ info->spd[channel][slot][TIMEBASE_DIVISOR];
+ cycletime = max(cycletime, timebase * info->spd[channel][slot][CYCLETIME]);
+ cas_latency_time = max(cas_latency_time, timebase *
+ info->spd[channel][slot][CAS_LATENCY_TIME]);
+ }
if (cycletime > min_cycletime[0])
die("RAM init: Decoded SPD DRAM freq is slower than the controller minimum!");
for (clock_speed_index = 0; clock_speed_index < 3; clock_speed_index++) {
@@ -633,128 +651,125 @@
extended_silicon_revision = info->silicon_revision;
if (info->silicon_revision == 0)
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
+ FOR_ALL_SLOTS(channel, slot) {
+ if ((info->spd[channel][slot][MODULE_TYPE] & 0xF) == 3)
+ extended_silicon_revision = 4;
+ }
+
+ FOR_EACH_CHANNEL(channel) {
+ FOR_ALL_POPULATED_RANKS_ON_CHANNEL(info, channel, slot, rank) {
+ int card_timing_2;
+ if (!info->populated_ranks[channel][slot][rank])
+ continue;
+
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ int tm_reg;
+ int card_timing;
+
+ card_timing = 0;
if ((info->
- spd[channel][slot][MODULE_TYPE] & 0xF) ==
- 3)
- extended_silicon_revision = 4;
-
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_SLOTS; rank++) {
- int card_timing_2;
- if (!info->populated_ranks[channel][slot][rank])
- continue;
-
- for (lane = 0; lane < 9; lane++) {
- int tm_reg;
- int card_timing;
-
- card_timing = 0;
- if ((info->
- spd[channel][slot][MODULE_TYPE] &
- 0xF) == 3) {
- int reference_card;
- reference_card =
- info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] &
- 0x1f;
- if (reference_card == 3)
- card_timing =
- u16_ffd1188[0][lane]
- [info->
- clock_speed_index];
- if (reference_card == 5)
- card_timing =
- u16_ffd1188[1][lane]
- [info->
- clock_speed_index];
- }
-
- info->training.
- lane_timings[0][channel][slot][rank]
- [lane] =
- u8_FFFD1218[info->
- clock_speed_index];
- info->training.
- lane_timings[1][channel][slot][rank]
- [lane] = 256;
-
- for (tm_reg = 2; tm_reg < 4; tm_reg++)
- info->training.
- lane_timings[tm_reg]
- [channel][slot][rank][lane]
- =
- u8_FFFD1240[channel]
- [extended_silicon_revision]
- [lane][2 * slot +
- rank][info->
- clock_speed_index]
- + info->max4048[channel]
- +
- u8_FFFD0C78[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][slot]
- [rank][info->
- clock_speed_index]
- + card_timing;
- for (tm_reg = 0; tm_reg < 4; tm_reg++)
- write_500(info, channel,
- info->training.
- lane_timings[tm_reg]
- [channel][slot][rank]
- [lane],
- get_timing_register_addr
- (lane, tm_reg, slot,
- rank), 9, 0);
+ spd[channel][slot][MODULE_TYPE] &
+ 0xF) == 3) {
+ int reference_card;
+ reference_card =
+ info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] &
+ 0x1f;
+ if (reference_card == 3)
+ card_timing =
+ u16_ffd1188[0][lane]
+ [info->
+ clock_speed_index];
+ if (reference_card == 5)
+ card_timing =
+ u16_ffd1188[1][lane]
+ [info->
+ clock_speed_index];
}
- card_timing_2 = 0;
- if (!(extended_silicon_revision != 4
- || (info->
- populated_ranks_mask[channel] & 5) ==
- 5)) {
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] & 0x1F)
- == 3)
- card_timing_2 =
- u16_FFFE0EB8[0][info->
- clock_speed_index];
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] & 0x1F)
- == 5)
- card_timing_2 =
- u16_FFFE0EB8[1][info->
- clock_speed_index];
- }
+ info->training.
+ lane_timings[0][channel][slot][rank]
+ [lane] =
+ u8_FFFD1218[info->
+ clock_speed_index];
+ info->training.
+ lane_timings[1][channel][slot][rank]
+ [lane] = 256;
- for (i = 0; i < 3; i++)
+ for (tm_reg = 2; tm_reg < 4; tm_reg++)
+ info->training.
+ lane_timings[tm_reg]
+ [channel][slot][rank][lane]
+ =
+ u8_FFFD1240[channel]
+ [extended_silicon_revision]
+ [lane][2 * slot +
+ rank][info->
+ clock_speed_index]
+ + info->max4048[channel]
+ +
+ u8_FFFD0C78[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][slot]
+ [rank][info->
+ clock_speed_index]
+ + card_timing;
+ for (tm_reg = 0; tm_reg < 4; tm_reg++)
write_500(info, channel,
- (card_timing_2 +
- info->max4048[channel]
- +
- u8_FFFD0EF8[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][info->
- clock_speed_index]),
- u16_fffd0c50[i][slot][rank],
- 8, 1);
- write_500(info, channel,
- (info->max4048[channel] +
- u8_FFFD0C78[channel]
- [extended_silicon_revision][info->
- mode4030
- [channel]]
- [slot][rank][info->
- clock_speed_index]),
- u16_fffd0c70[slot][rank], 7, 1);
+ info->training.
+ lane_timings[tm_reg]
+ [channel][slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, tm_reg, slot,
+ rank), 9, 0);
}
+
+ card_timing_2 = 0;
+ if (!(extended_silicon_revision != 4
+ || (info->
+ populated_ranks_mask[channel] & 5) ==
+ 5)) {
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] & 0x1F)
+ == 3)
+ card_timing_2 =
+ u16_FFFE0EB8[0][info->
+ clock_speed_index];
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] & 0x1F)
+ == 5)
+ card_timing_2 =
+ u16_FFFE0EB8[1][info->
+ clock_speed_index];
+ }
+
+ for (i = 0; i < 3; i++)
+ write_500(info, channel,
+ (card_timing_2 +
+ info->max4048[channel]
+ +
+ u8_FFFD0EF8[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][info->
+ clock_speed_index]),
+ u16_fffd0c50[i][slot][rank],
+ 8, 1);
+ write_500(info, channel,
+ (info->max4048[channel] +
+ u8_FFFD0C78[channel]
+ [extended_silicon_revision][info->
+ mode4030
+ [channel]]
+ [slot][rank][info->
+ clock_speed_index]),
+ u16_fffd0c70[slot][rank], 7, 1);
+ }
if (!info->populated_ranks_mask[channel])
continue;
for (i = 0; i < 3; i++)
@@ -828,12 +843,12 @@
some_delay_3_ps_rounded = 0;
extended_silicon_revision = info->silicon_revision;
if (!info->silicon_revision)
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- if ((info->
- spd[channel][slot][MODULE_TYPE] & 0xF) ==
- 3)
- extended_silicon_revision = 4;
+ FOR_ALL_SLOTS(channel, slot) {
+ if ((info->
+ spd[channel][slot][MODULE_TYPE] & 0xF) ==
+ 3)
+ extended_silicon_revision = 4;
+ }
if (info->board_lane_delay[7] < 5)
info->board_lane_delay[7] = 5;
info->revision_flag_1 = 2;
@@ -914,7 +929,7 @@
|| (count_ranks_in_channel(info, 1) ==
2)) ? 2 : 3;
}
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
int max_of_unk;
int min_of_unk_2;
@@ -945,67 +960,66 @@
[i];
else
unk1 = 0;
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++) {
- int a = 0;
- int b = 0;
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ int a = 0;
+ int b = 0;
- if (!info->
- populated_ranks[channel][slot]
- [rank])
- continue;
- if (extended_silicon_revision == 4
- && (info->
- populated_ranks_mask[channel] &
- 5) != 5) {
+ if (!info->
+ populated_ranks[channel][slot]
+ [rank])
+ continue;
+ if (extended_silicon_revision == 4
+ && (info->
+ populated_ranks_mask[channel] &
+ 5) != 5) {
+ if ((info->
+ spd[channel][slot]
+ [REFERENCE_RAW_CARD_USED] &
+ 0x1F) == 3) {
+ a = u16_ffd1178[0]
+ [info->
+ clock_speed_index];
+ b = u16_fe0eb8[0][info->
+ clock_speed_index];
+ } else
if ((info->
spd[channel][slot]
- [REFERENCE_RAW_CARD_USED] &
- 0x1F) == 3) {
- a = u16_ffd1178[0]
- [info->
- clock_speed_index];
- b = u16_fe0eb8[0][info->
- clock_speed_index];
- } else
- if ((info->
- spd[channel][slot]
- [REFERENCE_RAW_CARD_USED]
- & 0x1F) == 5) {
+ [REFERENCE_RAW_CARD_USED]
+ & 0x1F) == 5) {
a = u16_ffd1178[1]
- [info->
- clock_speed_index];
+ [info->
+ clock_speed_index];
b = u16_fe0eb8[1][info->
clock_speed_index];
}
- }
- min_of_unk_2 = min(min_of_unk_2, a);
- min_of_unk_2 = min(min_of_unk_2, b);
- if (rank == 0) {
- sum += a;
- count++;
- }
- {
- int t;
- t = b +
- u8_FFFD0EF8[channel]
- [extended_silicon_revision]
- [info->
- mode4030[channel]][info->
- clock_speed_index];
- if (unk1 >= t)
- max_of_unk =
- max(max_of_unk,
- unk1 - t);
- }
}
+ min_of_unk_2 = min(min_of_unk_2, a);
+ min_of_unk_2 = min(min_of_unk_2, b);
+ if (rank == 0) {
+ sum += a;
+ count++;
+ }
+ {
+ int t;
+ t = b +
+ u8_FFFD0EF8[channel]
+ [extended_silicon_revision]
+ [info->
+ mode4030[channel]][info->
+ clock_speed_index];
+ if (unk1 >= t)
+ max_of_unk =
+ max(max_of_unk,
+ unk1 - t);
+ }
+ }
{
int t =
- u8_FFFD17E0[channel]
- [extended_silicon_revision][info->
- mode4030
- [channel]]
- [info->clock_speed_index] + min_of_unk_2;
+ u8_FFFD17E0[channel]
+ [extended_silicon_revision][info->
+ mode4030
+ [channel]]
+ [info->clock_speed_index] + min_of_unk_2;
if (unk1 >= t)
max_of_unk = max(max_of_unk, unk1 - t);
}
@@ -1080,7 +1094,7 @@
} else {
write_recovery = 6;
}
- FOR_POPULATED_RANKS {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
auto_self_refresh &=
(info->spd[channel][slot][THERMAL_AND_REFRESH] >> 2) & 1;
self_refresh_temperature &=
@@ -1097,7 +1111,7 @@
total_rank = 0;
- for (channel = NUM_CHANNELS - 1; channel >= 0; channel--) {
+ FOR_EACH_CHANNEL_BACKWARDS(channel) {
int rtt, rtt_wr = MR2_RTT_WR_DISABLED;
int rzq_reg58e;
@@ -1126,31 +1140,31 @@
MCHBAR16(0x58e + (channel << 10)) = rzq_reg58e | 0x82;
MCHBAR16(0x590 + (channel << 10)) = 0x1282;
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- if (info->populated_ranks[channel][slot][rank]) {
- jedec_read(info, channel, slot, rank,
- total_rank, 0x28,
- rtt_wr | (info->
- clock_speed_index
- << 3)
- | (auto_self_refresh << 6) |
- (self_refresh_temperature <<
- 7));
- jedec_read(info, channel, slot, rank,
- total_rank, 0x38, 0);
- jedec_read(info, channel, slot, rank,
- total_rank, 0x18,
- rtt | MR1_ODS34OHM);
- jedec_read(info, channel, slot, rank,
- total_rank, 6,
- (dll_on << 12) |
- (write_recovery << 9)
- | ((info->cas_latency - 4) <<
- 4) | MR0_BT_INTERLEAVED |
- MR0_DLL_RESET_ON);
- total_rank++;
- }
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ if (info->populated_ranks[channel][slot][rank]) {
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x28,
+ rtt_wr | (info->
+ clock_speed_index
+ << 3)
+ | (auto_self_refresh << 6) |
+ (self_refresh_temperature <<
+ 7));
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x38, 0);
+ jedec_read(info, channel, slot, rank,
+ total_rank, 0x18,
+ rtt | MR1_ODS34OHM);
+ jedec_read(info, channel, slot, rank,
+ total_rank, 6,
+ (dll_on << 12) |
+ (write_recovery << 9)
+ | ((info->cas_latency - 4) <<
+ 4) | MR0_BT_INTERLEAVED |
+ MR0_DLL_RESET_ON);
+ total_rank++;
+ }
+ }
}
}
@@ -1160,7 +1174,7 @@
unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */
unsigned int channel_0_non_interleaved;
- FOR_ALL_RANKS {
+ FOR_ALL_RANKS(channel, slot, rank) {
if (info->populated_ranks[channel][slot][rank]) {
total_mb[channel] +=
pre_jedec ? 256 : (256 << info->
@@ -1257,7 +1271,7 @@
}
if (MCHBAR8(0x2ca9) & 1)
some_delay_3_half_cycles = 3;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32_OR(0x220 + (channel << 10), 0x18001117);
MCHBAR32(0x224 + (channel << 10)) =
(info->max_slots_used_in_channel - 1) |
@@ -1314,7 +1328,7 @@
cas_latency_derived = info->cas_latency - info->clock_speed_index + 2;
if (info->clock_speed_index > 1)
cas_latency_derived++;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x240 + (channel << 10)) =
((info->clock_speed_index == 0) * 0x11000) |
0x1002100 | ((2 + info->clock_speed_index) << 4) |
@@ -1518,13 +1532,14 @@
if (capid0[2] & 2) {
info->silicon_revision = 0;
info->max_supported_clock_speed_index = 2;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
if (info->populated_ranks[channel][0][0]
&& (info->spd[channel][0][MODULE_TYPE] & 0xf) ==
3) {
info->silicon_revision = 2;
info->max_supported_clock_speed_index = 1;
}
+ }
} else {
switch (((capid0[2] >> 18) & 1) + 2 * ((capid0[1] >> 3) & 1)) {
case 1:
@@ -1556,19 +1571,19 @@
return;
for (tm = 0; tm < 4; tm++)
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- for (lane = 0; lane < 9; lane++)
- write_500(info, channel,
- info->
- cached_training->
- lane_timings[tm]
- [channel][slot][rank]
- [lane],
- get_timing_register_addr
- (lane, tm, slot,
- rank), 9, 0);
+ FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ write_500(info, channel,
+ info->
+ cached_training->
+ lane_timings[tm]
+ [channel][slot][rank]
+ [lane],
+ get_timing_register_addr
+ (lane, tm, slot,
+ rank), 9, 0);
+ }
+ }
write_1d0(info->cached_training->reg_178, 0x178, 7, 1);
write_1d0(info->cached_training->reg_10b, 0x10b, 6, 1);
}
@@ -1577,10 +1592,10 @@
{
int channel, slot, rank, lane, i;
printk(RAM_DEBUG, "Timings:\n");
- FOR_POPULATED_RANKS {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel,
slot, rank);
- for (lane = 0; lane < 9; lane++) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
printk(RAM_DEBUG, "lane %d: ", lane);
for (i = 0; i < 4; i++) {
printk(RAM_DEBUG, "%x (%x) ",
@@ -1610,16 +1625,19 @@
int channel, slot, rank, lane, i;
train = info->training;
- FOR_POPULATED_RANKS for (lane = 0; lane < 9; lane++)
- for (i = 0; i < 4; i++)
- train.lane_timings[i][channel][slot][rank][lane] =
- read_500(info, channel,
- get_timing_register_addr(lane, i, slot,
- rank), 9);
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ for (i = 0; i < 4; i++)
+ train.lane_timings[i][channel][slot][rank][lane] =
+ read_500(info, channel,
+ get_timing_register_addr(lane, i, slot,
+ rank), 9);
+ }
+ }
train.reg_178 = read_1d0(0x178, 7);
train.reg_10b = read_1d0(0x10b, 6);
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
u32 reg32;
reg32 = MCHBAR32((channel << 10) + 0x274);
train.reg274265[channel][0] = reg32 >> 16;
@@ -1912,27 +1930,28 @@
{
int i, channel, slot, rank, lane;
for (i = 0; i < 2; i++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- for (lane = 0; lane < 9; lane++)
- info->training.
- lane_timings[0][i][slot][rank][lane]
- = 32;
+ FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ info->training.
+ lane_timings[0][i][slot][rank][lane]
+ = 32;
+ }
+ }
- for (i = 1; i < 4; i++)
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- for (lane = 0; lane < 9; lane++) {
- info->training.
- lane_timings[i][channel]
- [slot][rank][lane] =
- read_500(info, channel,
- get_timing_register_addr
- (lane, i, slot,
- rank), 9)
- + (i == 1) * 11; // !!!!
- }
+ for (i = 1; i < 4; i++) {
+ FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ info->training.
+ lane_timings[i][channel]
+ [slot][rank][lane] =
+ read_500(info, channel,
+ get_timing_register_addr
+ (lane, i, slot,
+ rank), 9)
+ + (i == 1) * 11; // !!!!
+ }
+ }
+ }
}
@@ -2186,7 +2205,7 @@
{
int lane;
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
int is_fail = (fail_mask >> lane) & 1;
switch (state[lane]) {
case BEFORE_USABLE:
@@ -2250,7 +2269,7 @@
if (!first_run) {
int is_all_ok = 1;
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
if (timings[reg_178][channel][slot][rank][lane].
smallest ==
timings[reg_178][channel][slot][rank][lane].
@@ -2261,6 +2280,7 @@
largest = 0;
is_all_ok = 0;
}
+ }
if (is_all_ok) {
for (i = 0; i < 8; i++)
state[i] = COMPLETE;
@@ -2280,7 +2300,7 @@
if (reg1b3) {
write_1d0(0, 0x1b3, 6, 1);
write_1d0(0, 0x1a3, 6, 1);
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
if (state[lane] == COMPLETE) {
timings[reg_178][channel][slot][rank][lane].
smallest =
@@ -2299,7 +2319,7 @@
}
if (!first_run) {
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
if (state[lane] == COMPLETE) {
write_500(info, channel,
timings[reg_178][channel][slot][rank]
@@ -2324,7 +2344,7 @@
num_successfully_checked[lane] = 0;
} else
num_successfully_checked[lane] = -1;
-
+ }
do {
u8 failmask = 0;
for (i = 0; i < niter; i++) {
@@ -2338,7 +2358,7 @@
1);
}
MCHBAR32_OR(0xfb0, 0x00030000);
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
if (timings[reg_178][channel]
@@ -2395,11 +2415,12 @@
num_successfully_checked[lane]
++;
}
+ }
}
while (!check_bounded(num_successfully_checked, 2))
;
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
if (state[lane] == COMPLETE) {
write_500(info, channel,
timings[reg_178][channel][slot][rank]
@@ -2424,6 +2445,7 @@
num_successfully_checked[lane] = 0;
} else
num_successfully_checked[lane] = -1;
+ }
do {
int failmask = 0;
@@ -2439,7 +2461,7 @@
}
MCHBAR32_OR(0xfb0, 0x00030000);
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
if (num_successfully_checked[lane] != 0xffff) {
if ((1 << lane) & failmask) {
if (timings[reg_178][channel]
@@ -2502,7 +2524,7 @@
while (!check_bounded(num_successfully_checked, 3))
;
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
info->training.
lane_timings[0][channel][slot][rank][lane],
@@ -2537,28 +2559,30 @@
write_1d0(val, 0x10b, 6, 1);
- FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 9; lane++) {
- u16 reg_500;
- reg_500 = read_500(info, channel,
- get_timing_register_addr(lane, 0, slot,
- rank), 9);
- if (val == 1) {
- if (lut16[info->clock_speed_index] <= reg_500)
- reg_500 -= lut16[info->clock_speed_index];
- else
- reg_500 = 0;
- } else {
- reg_500 += lut16[info->clock_speed_index];
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
+ u16 reg_500;
+ reg_500 = read_500(info, channel,
+ get_timing_register_addr(lane, 0, slot,
+ rank), 9);
+ if (val == 1) {
+ if (lut16[info->clock_speed_index] <= reg_500)
+ reg_500 -= lut16[info->clock_speed_index];
+ else
+ reg_500 = 0;
+ } else {
+ reg_500 += lut16[info->clock_speed_index];
+ }
+ write_500(info, channel, reg_500,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
}
- write_500(info, channel, reg_500,
- get_timing_register_addr(lane, 0, slot, rank), 9, 1);
}
}
static void set_ecc(int onoff)
{
int channel;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
u8 t;
t = MCHBAR8((channel << 10) + 0x5f8);
if (onoff)
@@ -2585,12 +2609,13 @@
{
int lane;
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
info->training.
lane_timings[type][channel][slot][rank][lane],
get_timing_register_addr(lane, type, slot, rank), 9,
0);
+ }
}
static void
@@ -2610,11 +2635,12 @@
memset(count, 0, sizeof(count));
- for (lane = 0; lane < 8; lane++)
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
info->training.
lane_timings[2][channel][slot][rank][lane] + 32,
get_timing_register_addr(lane, 3, slot, rank), 9, 1);
+ }
for (timing_offset = 0; !validate_state(state) && timing_offset < 64;
timing_offset++) {
@@ -2634,7 +2660,7 @@
if (!validate_state(state))
die("Couldn't discover DRAM timings (1)\n");
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
u8 bias = 0;
if (info->silicon_revision) {
@@ -2758,13 +2784,15 @@
reg178 < reg178_max[info->clock_speed_index];
reg178 += reg178_step[info->clock_speed_index]) {
margin[reg178] = -1;
- FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
- int curmargin =
- timings[reg178][channel][slot][rank][lane].largest -
- timings[reg178][channel][slot][rank][lane].
- smallest + 1;
- if (curmargin < margin[reg178])
- margin[reg178] = curmargin;
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_EACH_LANE(lane) {
+ int curmargin =
+ timings[reg178][channel][slot][rank][lane].largest -
+ timings[reg178][channel][slot][rank][lane].
+ smallest + 1;
+ if (curmargin < margin[reg178])
+ margin[reg178] = curmargin;
+ }
}
if (margin[reg178] >= STANDARD_MIN_MARGIN) {
u16 weight;
@@ -2816,29 +2844,28 @@
if (!info->cached_training)
return 0;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- for (lane = 0; lane < 8 + info->use_ecc; lane++) {
- u16 cached_value, estimation_value;
- cached_value =
- info->cached_training->
- lane_timings[1][channel][slot][rank]
- [lane];
- if (cached_value >= 0x18
- && cached_value <= 0x1E7) {
- estimation_value =
- info->training.
- lane_timings[1][channel]
- [slot][rank][lane];
- if (estimation_value <
- cached_value - 24)
- return 0;
- if (estimation_value >
- cached_value + 24)
- return 0;
- }
- }
+ FOR_ALL_RANKS(channel, slot, rank) {
+ for (lane = 0; lane < 8 + info->use_ecc; lane++) {
+ u16 cached_value, estimation_value;
+ cached_value =
+ info->cached_training->
+ lane_timings[1][channel][slot][rank]
+ [lane];
+ if (cached_value >= 0x18
+ && cached_value <= 0x1E7) {
+ estimation_value =
+ info->training.
+ lane_timings[1][channel]
+ [slot][rank][lane];
+ if (estimation_value <
+ cached_value - 24)
+ return 0;
+ if (estimation_value >
+ cached_value + 24)
+ return 0;
+ }
+ }
+ }
return 1;
}
@@ -2885,9 +2912,9 @@
it still works whereas with j == 1 we check that just outside of
bound we fail.
*/
- FOR_POPULATED_RANKS_BACKWARDS {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
for (i = 0; i < 2; i++) {
- for (lane = 0; lane < 8; lane++) {
+ FOR_EACH_LANE(lane) {
write_500(info, channel,
info->cached_training->
timing2_bounds[channel][slot]
@@ -2982,7 +3009,7 @@
return 1;
fail:
- FOR_POPULATED_RANKS {
+ FOR_ALL_POPULATED_RANKS(info, channel, slot, rank) {
write_500_timings_type(info, channel, slot, rank, 1);
write_500_timings_type(info, channel, slot, rank, 2);
write_500_timings_type(info, channel, slot, rank, 3);
@@ -3026,7 +3053,7 @@
}
set_ecc(0);
- FOR_POPULATED_RANKS_BACKWARDS {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
int i;
write_500_timings_type(info, channel, slot, rank, 0);
@@ -3051,9 +3078,8 @@
reg_178 += reg178_step[info->clock_speed_index]) {
totalrank = 0;
set_178(reg_178);
- for (channel = NUM_CHANNELS - 1; channel >= 0; channel--)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++) {
+ FOR_EACH_CHANNEL_BACKWARDS(channel) {
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
memset(&timings[reg_178][channel][slot]
[rank][0].smallest, 0, 16);
if (info->
@@ -3067,34 +3093,37 @@
timings);
totalrank++;
}
- }
+ }
+ }
}
reg178_center = choose_reg178(info, timings);
- FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
- info->training.timing_bounds[0][channel][slot][rank][lane].
- smallest =
- timings[info->training.
- reg178_smallest][channel][slot][rank][lane].
- smallest;
- info->training.timing_bounds[0][channel][slot][rank][lane].
- largest =
- timings[info->training.
- reg178_smallest][channel][slot][rank][lane].largest;
- info->training.timing_bounds[1][channel][slot][rank][lane].
- smallest =
- timings[info->training.
- reg178_largest][channel][slot][rank][lane].smallest;
- info->training.timing_bounds[1][channel][slot][rank][lane].
- largest =
- timings[info->training.
- reg178_largest][channel][slot][rank][lane].largest;
- info->training.timing_offset[channel][slot][rank][lane] =
- info->training.lane_timings[1][channel][slot][rank][lane]
- -
- info->training.lane_timings[0][channel][slot][rank][lane] +
- 64;
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_EACH_LANE(lane) {
+ info->training.timing_bounds[0][channel][slot][rank][lane].
+ smallest =
+ timings[info->training.
+ reg178_smallest][channel][slot][rank][lane].
+ smallest;
+ info->training.timing_bounds[0][channel][slot][rank][lane].
+ largest =
+ timings[info->training.
+ reg178_smallest][channel][slot][rank][lane].largest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].
+ smallest =
+ timings[info->training.
+ reg178_largest][channel][slot][rank][lane].smallest;
+ info->training.timing_bounds[1][channel][slot][rank][lane].
+ largest =
+ timings[info->training.
+ reg178_largest][channel][slot][rank][lane].largest;
+ info->training.timing_offset[channel][slot][rank][lane] =
+ info->training.lane_timings[1][channel][slot][rank][lane]
+ -
+ info->training.lane_timings[0][channel][slot][rank][lane] +
+ 64;
+ }
}
if (info->silicon_revision == 1
@@ -3108,19 +3137,18 @@
reg_178 <= reg178_center + 18; reg_178 += 18) {
totalrank = 0;
set_178(reg_178);
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++) {
- if (info->
- populated_ranks[1][slot][rank]) {
- train_ram_at_178(info, 1, slot,
- rank,
- totalrank,
- reg_178, 0,
- niter,
- timings);
- totalrank++;
- }
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ if (info->
+ populated_ranks[1][slot][rank]) {
+ train_ram_at_178(info, 1, slot,
+ rank,
+ totalrank,
+ reg_178, 0,
+ niter,
+ timings);
+ totalrank++;
}
+ }
}
ranks_after_channel1 = totalrank;
@@ -3128,18 +3156,18 @@
reg_178 <= reg178_center + 12; reg_178 += 12) {
totalrank = ranks_after_channel1;
set_178(reg_178);
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- if (info->
- populated_ranks[0][slot][rank]) {
- train_ram_at_178(info, 0, slot,
- rank,
- totalrank,
- reg_178, 0,
- niter,
- timings);
- totalrank++;
- }
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ if (info->
+ populated_ranks[0][slot][rank]) {
+ train_ram_at_178(info, 0, slot,
+ rank,
+ totalrank,
+ reg_178, 0,
+ niter,
+ timings);
+ totalrank++;
+ }
+ }
}
} else {
@@ -3147,7 +3175,7 @@
reg_178 <= reg178_center + 12; reg_178 += 12) {
totalrank = 0;
set_178(reg_178);
- FOR_POPULATED_RANKS_BACKWARDS {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
train_ram_at_178(info, channel, slot, rank,
totalrank, reg_178, 0, niter,
timings);
@@ -3157,25 +3185,27 @@
}
set_178(reg178_center);
- FOR_POPULATED_RANKS_BACKWARDS for (lane = 0; lane < 8; lane++) {
- u16 tm0;
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
+ FOR_EACH_LANE(lane) {
+ u16 tm0;
- tm0 =
- choose_training(info, channel, slot, rank, lane, timings,
- reg178_center);
- write_500(info, channel, tm0,
- get_timing_register_addr(lane, 0, slot, rank), 9, 1);
- write_500(info, channel,
- tm0 +
- info->training.
- lane_timings[1][channel][slot][rank][lane] -
- info->training.
- lane_timings[0][channel][slot][rank][lane],
- get_timing_register_addr(lane, 1, slot, rank), 9, 1);
+ tm0 =
+ choose_training(info, channel, slot, rank, lane, timings,
+ reg178_center);
+ write_500(info, channel, tm0,
+ get_timing_register_addr(lane, 0, slot, rank), 9, 1);
+ write_500(info, channel,
+ tm0 +
+ info->training.
+ lane_timings[1][channel][slot][rank][lane] -
+ info->training.
+ lane_timings[0][channel][slot][rank][lane],
+ get_timing_register_addr(lane, 1, slot, rank), 9, 1);
+ }
}
totalrank = 0;
- FOR_POPULATED_RANKS_BACKWARDS {
+ FOR_ALL_POPULATED_RANKS_BACKWARDS(info, channel, slot, rank) {
try_timing_offsets(info, channel, slot, rank, totalrank);
totalrank++;
}
@@ -3525,14 +3555,14 @@
if (info->revision < 8)
return 256;
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- if (info->populated_ranks[channel][slot][rank])
- for (lane = 0; lane < 8 + info->use_ecc; lane++)
- ret = max(ret, read_500(info, channel,
- get_timing_register_addr
- (lane, 0, slot,
- rank), 9));
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ if (info->populated_ranks[channel][slot][rank])
+ for (lane = 0; lane < 8 + info->use_ecc; lane++)
+ ret = max(ret, read_500(info, channel,
+ get_timing_register_addr
+ (lane, 0, slot,
+ rank), 9));
+ }
return ret;
}
@@ -3546,7 +3576,7 @@
delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info);
info->training.reg2ca9_bit0 = 0;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
cycletime_ps =
900000 / lcm(2 * info->fsb_frequency, frequency_11(info));
delay_d_ps =
@@ -3634,7 +3664,7 @@
{
int channel;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32((channel << 10) + 0x274) =
(info->cached_training->reg274265[channel][0] << 16) |
info->cached_training->reg274265[channel][1];
@@ -3768,8 +3798,8 @@
memset(&info.populated_ranks, 0, sizeof(info.populated_ranks));
info.use_ecc = 1;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++) {
+ FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_SLOT(slot) {
int v;
int try;
int addr;
@@ -3846,16 +3876,17 @@
0x18))
info.use_ecc = 0;
}
+ }
gav(0x55);
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
int v = 0;
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- v |= info.
- populated_ranks[channel][slot][rank]
- << (2 * slot + rank);
+ FOR_ALL_RANKS_ON_CHANNEL(slot, rank) {
+ v |= info.
+ populated_ranks[channel][slot][rank]
+ << (2 * slot + rank);
+ }
info.populated_ranks_mask[channel] = v;
}
@@ -4265,10 +4296,11 @@
MCHBAR32(0x160) = 0x5ffffff;
MCHBAR32_AND_OR(0x114, 0, 0xc2024440); // !!!!
MCHBAR32_AND_OR(0x118, 0, 0x4); // !!!!
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x260 + (channel << 10)) = 0x30809ff |
((info.populated_ranks_mask[channel] & 3) << 20);
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ }
+ FOR_EACH_CHANNEL(channel) {
MCHBAR16(0x31c + (channel << 10)) = 0x101;
MCHBAR16(0x360 + (channel << 10)) = 0x909;
MCHBAR16(0x3a4 + (channel << 10)) = 0x101;
@@ -4296,7 +4328,7 @@
populated_ranks[0]
[0][0]) << 0),
0x1d1, 3, 1);
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR16(0x38e + (channel << 10)) = 0x5f5f;
MCHBAR16(0x3d2 + (channel << 10)) = 0x5f5f;
}
@@ -4312,13 +4344,14 @@
write_1d0(0x0, 0xeb, 3, 1);
write_1d0(0x0, 0xf3, 6, 1);
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (lane = 0; lane < 9; lane++) {
+ FOR_EACH_CHANNEL(channel) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
u16 addr = 0x125 + get_lane_offset(0, 0, lane);
u8 a;
a = read_500(&info, channel, addr, 6); // = 0x20040080 //!!!!
write_500(&info, channel, a, addr, 6, 1);
}
+ }
udelay(1000);
@@ -4333,11 +4366,9 @@
}
int tm;
info.training = *info.cached_training;
- for (tm = 0; tm < 4; tm++)
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- for (lane = 0; lane < 9; lane++)
+ for (tm = 0; tm < 4; tm++) {
+ FOR_ALL_RANKS(channel, slot, rank) {
+ FOR_EACH_LANE_WITH_ECC(lane) {
write_500(&info,
channel,
info.training.
@@ -4349,6 +4380,9 @@
(lane, tm,
slot, rank),
9, 0);
+ }
+ }
+ }
write_1d0(info.cached_training->reg_178, 0x178, 7, 1);
write_1d0(info.cached_training->reg_10b, 0x10b, 6, 1);
}
@@ -4374,9 +4408,10 @@
read_1d0(0x328, 6); // = 0xfa018080 // !!!!
write_1d0(7, 0x328, 6, 1);
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
set_4cf(&info, channel,
info.populated_ranks[channel][0][0] ? 8 : 0);
+ }
read_1d0(0x116, 4); // = 0x4040432 // !!!!
write_1d0(2, 0x116, 4, 1);
@@ -4410,9 +4445,10 @@
1);
}
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
set_4cf(&info, channel,
info.populated_ranks[channel][0][0] ? 9 : 1);
+ }
rmw_1d0(0x116, 0xe, 1, 4, 1); // = 0x4040432 // !!!!
MCHBAR32(0x144); // !!!!
@@ -4424,9 +4460,10 @@
read_1d0(0x328, 6); // = 0xfa00c0c7 // !!!!
write_1d0(4, 0x328, 6, 1);
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
set_4cf(&info, channel,
info.populated_ranks[channel][0][0] ? 9 : 0);
+ }
MCHBAR32(0x130) = 0x11111301 | (info.populated_ranks[1][0][0] << 30) |
(info.populated_ranks[0][0][0] << 29);
@@ -4439,15 +4476,16 @@
read_1d0(0x14b, 7); // = 0x810231b0 // !!!!
write_1d0(0x35, 0x14b, 7, 1);
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
set_4cf(&info, channel,
info.populated_ranks[channel][0][0] ? 0xb : 0x2);
+ }
set_334(1);
MCHBAR8(0x1e8) = 0x4;
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
write_500(&info, channel,
0x3 & ~(info.populated_ranks_mask[channel]), 0x6b7, 2,
1);
@@ -4468,27 +4506,26 @@
MCHBAR8(0x271) = 0x2;
MCHBAR8(0x671) = 0x2;
MCHBAR8(0x1e8) = 0x4;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x294 + (channel << 10)) =
(info.populated_ranks_mask[channel] & 3) << 16;
+ }
MCHBAR32_AND_OR(0x134, 0xfc01ffff, 0x10000);
MCHBAR32_AND_OR(0x134, 0xfc85ffff, 0x850000);
- for (channel = 0; channel < NUM_CHANNELS; channel++)
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32_AND_OR(0x260 + (channel << 10), ~0xf00000, 0x8000000 |
((info.populated_ranks_mask[channel] & 3) << 20));
+ }
if (!s3resume)
jedec_init(&info);
int totalrank = 0;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- if (info.populated_ranks[channel][slot][rank]) {
- jedec_read(&info, channel, slot, rank,
- totalrank, 0xa, 0x400);
- totalrank++;
- }
+ FOR_ALL_POPULATED_RANKS(&info, channel, slot, rank) {
+ jedec_read(&info, channel, slot, rank,
+ totalrank, 0xa, 0x400);
+ totalrank++;
+ }
MCHBAR8(0x12c) = 0x9f;
@@ -4496,7 +4533,7 @@
MCHBAR8_AND_OR(0x671, 0, 0xe); // !!!!
if (!s3resume) {
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x294 + (channel << 10)) =
(info.populated_ranks_mask[channel] & 3) << 16;
MCHBAR16(0x298 + (channel << 10)) =
@@ -4523,15 +4560,14 @@
MCHBAR32(0x584) = 0xfffff;
MCHBAR32(0x984) = 0xfffff;
- for (channel = 0; channel < NUM_CHANNELS; channel++)
- for (slot = 0; slot < NUM_SLOTS; slot++)
- for (rank = 0; rank < NUM_RANKS; rank++)
- if (info.
- populated_ranks[channel][slot]
- [rank])
- config_rank(&info, s3resume,
- channel, slot,
- rank);
+ FOR_ALL_RANKS(channel, slot, rank) {
+ if (info.
+ populated_ranks[channel][slot]
+ [rank])
+ config_rank(&info, s3resume,
+ channel, slot,
+ rank);
+ }
MCHBAR8(0x243) = 0x1;
MCHBAR8(0x643) = 0x1;
@@ -4545,7 +4581,7 @@
/* end */
if (s3resume) {
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x294 + (channel << 10)) =
(info.populated_ranks_mask[channel] & 3) << 16;
MCHBAR16(0x298 + (channel << 10)) =
@@ -4627,7 +4663,7 @@
MCHBAR32(0x20) = 0x33001;
}
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32_AND(0x220 + (channel << 10), ~0x7770);
if (info.max_slots_used_in_channel == 1)
MCHBAR16_OR(0x237 + (channel << 10), 0x0201);
@@ -4654,7 +4690,7 @@
MCHBAR32(0x210) = (al << 16) | 0x20;
}
- for (channel = 0; channel < NUM_CHANNELS; channel++) {
+ FOR_EACH_CHANNEL(channel) {
MCHBAR32(0x288 + (channel << 10)) = 0x70605040;
MCHBAR32(0x28c + (channel << 10)) = 0xfffec080;
MCHBAR32(0x290 + (channel << 10)) = 0x282091c |
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