Subrata Banik has uploaded this change for review.

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soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T

It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.

FSPT_UPD.MicrocodeRegionBase∗∗ and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.

Since Gen-6 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.

Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/apollolake/fspcar.c
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/skylake/fspcar.c
4 files changed, 50 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37187/1
diff --git a/src/soc/intel/apollolake/fspcar.c b/src/soc/intel/apollolake/fspcar.c
index 8b1089f..129ff55 100644
--- a/src/soc/intel/apollolake/fspcar.c
+++ b/src/soc/intel/apollolake/fspcar.c
@@ -25,6 +25,17 @@
.FsptCommonUpd = {
.Revision = 0,
.Reserved = {0},
+ /*
+ * It is a requirement for firmware to have Firmware Interface Table
+ * (FIT), whioch contains pointers to each microcode update.
+ * The microcode update is loaded for all logical processors before
+ * cpu reset vector.
+ *
+ * All SoC since Gen-6 has above mechanism in place to load microcode
+ * even before hitting CPU reset vector. Hence skipping FSP-T loading
+ * microcode after CPU reset by passing '0' value to
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ */
.MicrocodeRegionBase = 0,
.MicrocodeRegionLength = 0,
.CodeRegionBase =
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c
index 653ba30..9826748 100644
--- a/src/soc/intel/cannonlake/bootblock/bootblock.c
+++ b/src/soc/intel/cannonlake/bootblock/bootblock.c
@@ -30,10 +30,19 @@
.Reserved = {0},
},
.FsptCoreUpd = {
- .MicrocodeRegionBase =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
- .MicrocodeRegionSize =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ /*
+ * It is a requirement for firmware to have Firmware Interface Table
+ * (FIT), whioch contains pointers to each microcode update.
+ * The microcode update is loaded for all logical processors before
+ * cpu reset vector.
+ *
+ * All SoC since Gen-6 has above mechanism in place to load microcode
+ * even before hitting CPU reset vector. Hence skipping FSP-T loading
+ * microcode after CPU reset by passing '0' value to
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ */
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index f75de1f..58ce3de 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -31,10 +31,19 @@
.Reserved = {0},
},
.FsptCoreUpd = {
- .MicrocodeRegionBase =
- (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
- .MicrocodeRegionLength =
- (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ /*
+ * It is a requirement for firmware to have Firmware Interface Table
+ * (FIT), whioch contains pointers to each microcode update.
+ * The microcode update is loaded for all logical processors before
+ * cpu reset vector.
+ *
+ * All SoC since Gen-6 has above mechanism in place to load microcode
+ * even before hitting CPU reset vector. Hence skipping FSP-T loading
+ * microcode after CPU reset by passing '0' value to
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ */
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
.CodeRegionBase =
(UINT32)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionLength = (UINT32)CONFIG_ROM_SIZE,
diff --git a/src/soc/intel/skylake/fspcar.c b/src/soc/intel/skylake/fspcar.c
index a4c3726..fff240a 100644
--- a/src/soc/intel/skylake/fspcar.c
+++ b/src/soc/intel/skylake/fspcar.c
@@ -23,10 +23,19 @@
.Reserved = {0},
},
.FsptCoreUpd = {
- .MicrocodeRegionBase =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
- .MicrocodeRegionSize =
- (uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+ /*
+ * It is a requirement for firmware to have Firmware Interface Table
+ * (FIT), whioch contains pointers to each microcode update.
+ * The microcode update is loaded for all logical processors before
+ * cpu reset vector.
+ *
+ * All SoC since Gen-6 has above mechanism in place to load microcode
+ * even before hitting CPU reset vector. Hence skipping FSP-T loading
+ * microcode after CPU reset by passing '0' value to
+ * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+ */
+ .MicrocodeRegionBase = 0,
+ .MicrocodeRegionLength = 0,
.CodeRegionBase =
(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Gerrit-Change-Number: 37187
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-MessageType: newchange