[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add STXS and CTXS method

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48943 )

Change subject: soc/amd/picasso: Add STXS and CTXS method
......................................................................

soc/amd/picasso: Add STXS and CTXS method

Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefit acpi.c to be more clear, too.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.

Signed-off-by: Eric Lai 
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
---
M src/soc/amd/common/acpi/gpio_bank_lib.asl
M src/soc/amd/picasso/acpi.c
2 files changed, 40 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48943/1

diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl
index 9686ddc..ab76418 100644
--- a/src/soc/amd/common/acpi/gpio_bank_lib.asl
+++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl
@@ -2,6 +2,8 @@

#include <soc/iomap.h>

+#define PAD_CFG0_TX_STATE 0x400000
+
 /* Get pin control MMIO address */
 Method (GPAD, 0x1)
 {
@@ -117,3 +119,31 @@
    /* Arg1 - Value for control register */
    GPSB (Arg0, 3, Arg1)
 }
+
+/*
+ * Set GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (STXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GPAD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	VAL0 |= PAD_CFG0_TX_STATE
+}
+
+/*
+ * Clear GPIO Tx Value
+ * Arg0 - GPIO Number
+ */
+Method (CTXS, 1, Serialized)
+{
+	OperationRegion (PREG, SystemMemory, GPAD (Arg0), 4)
+	Field (PREG, AnyAcc, NoLock, Preserve)
+	{
+		VAL0, 32
+	}
+	VAL0 &= ~PAD_CFG0_TX_STATE
+}
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 17940e9..63ba26c 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -474,45 +474,6 @@
    return 0;
 }

-static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
-{
-	if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
-		printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
-					" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
-		return -1;
-	}
-	uintptr_t addr = gpio_get_address(gpio_num);
-
-	/* Store (0x40, Local0) */
-	acpigen_write_store();
-	acpigen_write_integer(GPIO_PIN_OUT);
-	acpigen_emit_byte(LOCAL0_OP);
-
-	acpigen_soc_get_gpio_in_local5(addr);
-
-	if (val) {
-		/* Or (Local5, GPIO_PIN_OUT, Local5) */
-		acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP);
-	} else {
-		/* Not (GPIO_PIN_OUT, Local6) */
-		acpigen_write_not(LOCAL0_OP, LOCAL6_OP);
-
-		/* And (Local5, Local6, Local5) */
-		acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
-	}
-
-	/*
-	 *   SB.GPW2 (addr, Local5)
-	 * _SB.GPW2 is used to write control byte in control register
-	 * / byte 2. It is defined in gpio_lib.asl.
-	 */
-	acpigen_emit_namestring("\_SB.GPW2");
-	acpigen_write_integer(addr);
-	acpigen_emit_byte(LOCAL5_OP);
-
-	return 0;
-}
-
 int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
 {
    return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
@@ -523,12 +484,20 @@
    return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
 }

+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
 int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
 {
-	return acpigen_soc_set_gpio_val(gpio_num, 1);
+	return acpigen_soc_gpio_op("\_SB.STXS", gpio_num);
 }

int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 {
-	return acpigen_soc_set_gpio_val(gpio_num, 0);
+	return acpigen_soc_gpio_op("\_SB.CTXS", gpio_num);
 }