Krishna P Bhat D has uploaded this change for review.
mb/intel/adlrvp_n: Add initial code for adl-n variant board
This patch adds the following list of changes:
1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p
devictree.
2. Add support for 2 mainboards as ADL-N board with default EC (Windows
SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from
adlrvp-p.
Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
---
A src/mainboard/intel/adlrvp/devicetree_n.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb
3 files changed, 511 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/59915/1
diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb
new file mode 100644
index 0000000..2c45e85
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/devicetree_n.cb
@@ -0,0 +1,446 @@
+chip soc/intel/alderlake
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_B"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # Enable HECI1 interface
+ register "HeciEnabled" = "1"
+
+ # FSP configuration
+
+ # Enable CNVi BT
+ register "CnviBtCore" = "true"
+
+ # Sagv Configuration
+ register "SaGv" = "SaGv_Enabled"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # Enable PCH PCIE RP 5 using CLK 2
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .clk_src = 2,
+ .clk_req = 2,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
+
+ # Enable PCH PCIE RP 6 using CLK 5
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .clk_src = 5,
+ .clk_req = 5,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
+
+ # Enable PCH PCIE RP 8 using free running CLK (0x80)
+ # Clock source is shared with LAN and hence marked as free running.
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
+
+ # Enable PCH PCIE RP 9 using CLK 1
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .clk_src = 1,
+ .clk_req = 1,
+ .flags = PCIE_RP_CLK_REQ_DETECT,
+ }"
+
+ # Enable PCH PCIE RP 11 for optane
+ register "pch_pcie_rp[PCH_RP(11)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+
+ # Hybrid storage mode
+ register "HybridStorageMode" = "1"
+
+ # Enable CPU PCIE RP 1 using CLK 0
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .clk_req = 0,
+ .clk_src = 0,
+ }"
+
+ # Enable CPU PCIE RP 2 using CLK 3
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .clk_req = 3,
+ .clk_src = 3,
+ }"
+
+ # Enable CPU PCIE RP 3 using CLK 4
+ register "cpu_pcie_rp[CPU_RP(3)]" = "{
+ .clk_req = 4,
+ .clk_src = 4,
+ }"
+
+ register "SataSalpSupport" = "1"
+
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ }"
+
+ register "SataPortsDevSlp" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ }"
+
+ # Enable EDP in PortA
+ register "DdiPortAConfig" = "1"
+ # Enable HDMI in Port B
+ register "ddi_ports_config" = "{
+ [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
+ }"
+
+ # TCSS USB3
+ register "TcssAuxOri" = "0"
+
+ register "s0ix_enable" = "1"
+ register "dptf_enable" = "1"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 0,
+ [PchSerialIoIndexGSPI1] = 0,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # HD Audio
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
+ register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
+ register "PchHdaIDispCodecEnable" = "1"
+
+ register "CnviBtAudioOffload" = "true"
+
+ # Intel Common SoC Config
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device ref pcie5 on end
+ device ref igpu on end
+ device ref dtt on
+ chip drivers/intel/dptf
+
+ ## sensor information
+ register "options.tsr[0].desc" = ""Ambient""
+ register "options.tsr[1].desc" = ""Battery""
+ register "options.tsr[2].desc" = ""DDR""
+ register "options.tsr[3].desc" = ""Skin""
+
+ ## Active Policy
+ # TODO: below values are initial reference values only
+ register "policies.active" = "{
+ [0] = {
+ .target = DPTF_CPU,
+ .thresholds = {
+ TEMP_PCT(95, 90),
+ TEMP_PCT(90, 80),
+ }
+ },
+ [1] = {
+ .target = DPTF_TEMP_SENSOR_0,
+ .thresholds = {
+ TEMP_PCT(80, 90),
+ TEMP_PCT(70, 80),
+ }
+ }
+ }"
+
+ ## Passive Policy
+ # TODO: below values are initial reference values only
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
+ [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
+ }"
+
+ ## Critical Policy
+ # TODO: below values are initial reference values only
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
+ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
+ }"
+
+ ## Power Limits Control
+ register "controls.power_limits" = "{
+ .pl1 = {
+ .min_power = 35000,
+ .max_power = 45000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,
+ },
+ .pl2 = {
+ .min_power = 56000,
+ .max_power = 56000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,
+ }
+ }"
+
+ ## Charger Performance Control (Control, mA)
+ register "controls.charger_perf" = "{
+ [0] = { 255, 3000 },
+ [1] = { 24, 1500 },
+ [2] = { 16, 1000 },
+ [3] = { 8, 500 }
+ }"
+
+ ## Fan Performance Control (Percent, Speed, Noise, Power)
+ register "controls.fan_perf" = "{
+ [0] = { 90, 6700, 220, 2200, },
+ [1] = { 80, 5800, 180, 1800, },
+ [2] = { 70, 5000, 145, 1450, },
+ [3] = { 60, 4900, 115, 1150, },
+ [4] = { 50, 3838, 90, 900, },
+ [5] = { 40, 2904, 55, 550, },
+ [6] = { 30, 2337, 30, 300, },
+ [7] = { 20, 1608, 15, 150, },
+ [8] = { 10, 800, 10, 100, },
+ [9] = { 0, 0, 0, 50, }
+ }"
+
+ ## Fan options
+ register "options.fan.fine_grained_control" = "1"
+ register "options.fan.step_size" = "2"
+
+ device generic 0 alias dptf_policy on end
+ end
+ end
+ device ref ipu on
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "0x50000"
+ register "acpi_name" = ""IPU0""
+ register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+ register "cio2_num_ports" = "2"
+ register "cio2_lanes_used" = "{2,2}"
+ register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
+ register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
+ register "cio2_prt[0]" = "2"
+ register "cio2_prt[1]" = "1"
+ device generic 0 on end
+ end
+ end
+ device ref pcie4_0 on end
+ device ref pcie4_1 on end
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp1 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tbt_pcie_rp3 on end
+ device ref crashlog off end
+ device ref tcss_xhci on end
+ device ref tcss_dma0 on end
+ device ref tcss_dma1 on end
+ device ref xhci on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device ref usb2_port10 on end
+ end
+ end
+ end
+ end
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref i2c0 on end
+ device ref i2c1 on
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""OVTI5675""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM0""
+ register "chip_name" = ""Ov 5675 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+ register "ssdb.lanes_used" = "2"
+ register "ssdb.vcm_type" = "0x0C"
+ register "vcm_name" = ""VCM0""
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "450000000"
+ register "remote_name" = ""IPU0""
+
+ register "has_power_resource" = "1"
+ #Controls
+ register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
+ register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
+
+ #_ON
+ register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "3"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+ device i2c 36 on end
+ end
+ chip drivers/intel/mipi_camera
+ register "acpi_uid" = "3"
+ register "acpi_name" = ""VCM0""
+ register "chip_name" = ""DW AF VCM""
+ register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+ register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
+ register "vcm_compat" = ""dongwoon,dw9714""
+
+ device i2c 0C on end
+ end
+ end
+ device ref i2c2 on end
+ device ref i2c3 on end
+ device ref heci1 on end
+ device ref sata on end
+ device ref i2c5 on
+ chip drivers/intel/mipi_camera
+ register "acpi_hid" = ""OVTI5675""
+ register "acpi_uid" = "0"
+ register "acpi_name" = ""CAM1""
+ register "chip_name" = ""Ov 5675 Camera""
+ register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+ register "ssdb.lanes_used" = "2"
+ register "num_freq_entries" = "1"
+ register "link_freq[0]" = "450000000"
+ register "remote_name" = ""IPU0""
+
+ register "has_power_resource" = "1"
+ #Controls
+ register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
+ register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+ register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
+ register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
+
+ #_ON
+ register "on_seq.ops_cnt" = "4"
+ register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+ register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
+ register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
+ register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
+
+ #_OFF
+ register "off_seq.ops_cnt" = "3"
+ register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+
+ device i2c 36 on end
+ end
+ end
+ device ref pcie_rp1 on end
+ device ref pcie_rp3 on end # W/A to FSP issue
+ device ref pcie_rp4 on end # W/A to FSP issue
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp8 on end
+ device ref pcie_rp9 on end
+ device ref pcie_rp11 on end
+ device ref uart0 on end
+ device ref gspi0 on end
+ device ref p2sb on end
+ device ref hda on
+ chip drivers/intel/soundwire
+ device generic 0 on
+ chip drivers/soundwire/alc711
+ # SoundWire Link 0 ID 1
+ register "desc" = ""Headset Codec""
+ device generic 0.1 on end
+ end
+ end
+ end
+ end
+ device ref smbus on end
+ end
+end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb
new file mode 100644
index 0000000..e58e9fb
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n/overridetree.cb
@@ -0,0 +1,4 @@
+chip soc/intel/alderlake
+
+ device domain 0 on end
+end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb
new file mode 100644
index 0000000..e78d00f
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_n_ext_ec/overridetree.cb
@@ -0,0 +1,61 @@
+chip soc/intel/alderlake
+
+ device domain 0 on
+ device ref pch_espi on
+ chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ use conn2 as mux_conn[2]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ register "type" = "UPC_TYPE_HUB"
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""TypeC Port 1""
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""TypeC Port 2""
+ device ref tcss_usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""TypeC Port 3""
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref pmc hidden
+ # The pmc_mux chip driver is a placeholder for the
+ # PMC.MUX device in the ACPI hierarchy.
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "1"
+ register "usb3_port_number" = "1"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "2"
+ register "usb3_port_number" = "2"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 1 alias conn1 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ register "usb2_port_number" = "3"
+ register "usb3_port_number" = "3"
+ # SBU is fixed, HSL follows CC
+ register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+ device generic 2 alias conn2 on end
+ end
+ end
+ end
+ end
+ end
+end
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