Angel Pons has uploaded this change for review.

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cpu/intel/model_106cx: Factor out common Kconfig options

Note that selecting SSE2 implicitly selects SSE as well.

Change-Id: Ia7b34d19325b7c060ea5d02b49cae890629ccbcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/cpu/intel/model_106cx/Kconfig
M src/cpu/intel/socket_441/Kconfig
M src/cpu/intel/socket_FCBGA559/Kconfig
3 files changed, 5 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44246/1

diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 29e7a6c..dbe9b0a 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -5,6 +5,11 @@
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select CPU_X86_CACHE
+	select CPU_X86_LAPIC
+	select CPU_X86_MTRR
+	select CPU_X86_SMM
+	select CPU_X86_TSC
+	select MMX
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 8b4fdd1..0095c77 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -6,12 +6,6 @@
 config SOCKET_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select CPU_INTEL_MODEL_106CX
-	select CPU_X86_LAPIC
-	select CPU_X86_MTRR
-	select CPU_X86_SMM
-	select CPU_X86_TSC
-	select MMX
-	select SSE
 	select SETUP_XIP_CACHE
 
 config C_ENV_BOOTBLOCK_SIZE
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 71796ce..a1598220 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -8,12 +8,6 @@
 config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_106CX
-	select CPU_X86_LAPIC
-	select CPU_X86_MTRR
-	select CPU_X86_SMM
-	select CPU_X86_TSC
-	select MMX
-	select SSE
 	select CPU_HAS_L2_ENABLE_MSR
 
 config DCACHE_RAM_BASE

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