[coreboot-gerrit] Patch set updated for coreboot: c490805 armv7: Add CPU & MP primitive instructions

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4444

-gerrit

commit c490805f9c29a9a60e45d7d095b438387b9cc3a0
Author: Hung-Te Lin 
Date:   Thu Aug 8 11:27:27 2013 +0800

armv7: Add CPU & MP primitive instructions

To configure multi-processors, we need the intrinsic functions to get core ID,
    put core into idle state, and to wake up cores.

Change-Id: I87a62dab6efd6c8bb0c8e46373da7c7eb7b16b35
    Signed-off-by: Hung-Te Lin 
    Reviewed-on: https://gerrit.chromium.org/gerrit/65112
---
 src/arch/armv7/include/arch/cpu.h | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/armv7/include/arch/cpu.h
index f8b3005..efd2dc9 100644
--- a/src/arch/armv7/include/arch/cpu.h
+++ b/src/arch/armv7/include/arch/cpu.h
@@ -48,4 +48,40 @@ struct cpuinfo_arm {

#endif

+/* Primitives for CPU and MP cores. */
+
+/* read Main Id register (MIDR) */
+inline static uint32_t read_midr(void)
+{
+	uint32_t value;
+	asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value));
+	return value;
+}
+
+/* read Multiprocessor Affinity Register (MPIDR) */
+inline static uint32_t read_mpidr(void)
+{
+	uint32_t value;
+	asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value));
+	return value;
+}
+
+/* wait for interrupt. */
+inline static void wfi(void)
+{
+	asm volatile ("wfi" : : : "memory");
+}
+
+/* wait for event. */
+inline static void wfe(void)
+{
+	asm volatile ("wfe");
+}
+
+/* set event (to bring up cores in WFE state). */
+inline static void sev(void)
+{
+	asm volatile ("sev");
+}
+
 #endif /* __ARCH_CPU_H__ */