nsekar@codeaurora.org has uploaded this change for review.

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mistral: qcs405: Updated the layout info as in Gale

Changed the Mistral's layout as in Gale.

Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
---
M src/mainboard/google/mistral/chromeos.fmd
1 file changed, 24 insertions(+), 43 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30902/1

diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd
index e8b9978..a9bdd7b 100644
--- a/src/mainboard/google/mistral/chromeos.fmd
+++ b/src/mainboard/google/mistral/chromeos.fmd
@@ -1,52 +1,33 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2018, The Linux Foundation.  All rights reserved.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 and
-## only version 2 as published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
 FLASH@0x0 0x800000 {
-	WP_RO@0x0 0x300000 {
-		RO_SECTION@0x0 0x2FE000 {
-			BOOTBLOCK@0 248K
-			COREBOOT(CBFS)@0x3E000 0x1E0000
-			FMAP@0x21E000 0x1000
-			GBB@0x21F000 0xDEF00
-			RO_FRID@0x2FDF00 0x100
+	WP_RO@0x0 0x400000 {
+		RO_SECTION@0x0 0x3e0000 {
+			BOOTBLOCK@0 128K
+			COREBOOT(CBFS)@0x20000 0x2e0000
+			FMAP@0x300000 0x1000
+			GBB@0x301000 0xdef00
+			RO_FRID@0x3dff00 0x100
 		}
-		RO_VPD@0x2FE000 0x2000
+		RO_VPD@0x3e0000 0x20000
 	}
-
-	RW_NVRAM@0x300000 0x8000
-	RW_ELOG@0x308000 0x8000
-	RW_VPD@0x310000 0x8000
-	RW_CDT@0x318000 0x8000
-
-	RW_SECTION_A@0x320000 0x268000 {
+	RW_SECTION_A@0x400000 0x160000 {
 		VBLOCK_A@0x0 0x2000
-		FW_MAIN_A(CBFS)@0x2000 0x1E1F00
-		RW_FWID_A@0x1E3F00 0x100
-		RW_DDR_TRAINING_A@0x1E4000 0x4000
-		RW_XBL_BUFFER_A@0x1E8000 0x4000
+		FW_MAIN_A(CBFS)@0x2000 0x14df00
+		RW_FWID_A@0x14ff00 0x100
+		RW_SHARED@0x150000 0x10000 {
+			SHARED_DATA@0x0 0x10000
+		}
 	}
-
-	RW_SHARED@0x588000 0x10000 {
-		SHARED_DATA@0x0 0x10000
+	RW_GPT@0x560000 0x20000 {
+		RW_GPT_PRIMARY@0x0 0x10000
+		RW_GPT_SECONDARY@0x10000 0x10000
 	}
-
-	RW_SECTION_B@0x598000 0x268000 {
+	RW_SECTION_B@0x580000 0x160000 {
 		VBLOCK_B@0x0 0x2000
-		FW_MAIN_B(CBFS)@0x2000 0x1E1F00
-		RW_FWID_B@0x1E3F00 0x100
-		RW_DDR_TRAINING_B@0x1E4000 0x4000
-		RW_XBL_BUFFER_B@0x1E8000 0x4000
+		FW_MAIN_B(CBFS)@0x2000 0x14df00
+		RW_FWID_B@0x14ff00 0x100
 	}
+	RW_VPD@0x6e0000 0x8000
+	RW_ELOG@0x6e8000 0x8000
+	RW_NVRAM@0x6f0000 0x10000
+	RW_LEGACY(CBFS)@0x700000 0x100000
 }

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