Raul Rangel would like Aaron Durbin to review this change.
soc/amd/picasso: add Kconfig option to disable rom sharing
Add a knob for mainboards to request disablement of the SPI
flash ROM sharing in the chipset. The chipset allows the board
to share the SPI flash bus and needs a pin to perform the request.
If the board design does not employ SPI flash ROM sharing then it's
imperative to ensure this option is selected, especially if the
pin is being utilized by something else in the board design.
BUG=b:153502861
Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/southbridge.c
3 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/40869/1
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index dc33073..2fabac4 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -10,6 +10,8 @@
/* PCI registers for D14F3 */
#define LPC_PCI_CONTROL 0x40
#define LEGACY_DMA_EN BIT(2)
+#define VW_ROM_SHARING_EN BIT(3)
+#define EXT_ROM_SHARING_EN BIT(4)
#define LPC_IO_PORT_DECODE_ENABLE 0x44
#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0)
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index a37f543..a54a5f3 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -208,6 +208,14 @@
Picasso's LPC bus signals are MUXed with some of the EMMC signals.
Select this option if LPC signals are required.
+config DISABLE_SPI_FLASH_ROM_SHARING
+ def_bool n
+ help
+ Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
+ which indicates a board level ROM transaction request. This
+ removes arbitration with board and assumes the chipset controls
+ the SPI flash bus entirely.
+
config MAINBOARD_POWER_RESTORE
def_bool n
help
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 6bedab0..dd88ec9 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -330,11 +330,24 @@
printk(BIOS_DEBUG, "\n");
}
+static void disable_rom_sharing(void)
+{
+ u8 byte;
+
+ byte = pci_read_config8(SOC_LPC_DEV, LPC_PCI_CONTROL);
+ byte &= ~VW_ROM_SHARING_EN;
+ byte &= ~EXT_ROM_SHARING_EN;
+ pci_write_config8(SOC_LPC_DEV, LPC_PCI_CONTROL, byte);
+}
+
/* After console init */
void fch_early_init(void)
{
sb_print_pmxc0_status();
i2c_soc_early_init();
+
+ if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+ disable_rom_sharing();
}
void sb_enable(struct device *dev)
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