Attention is currently required from: Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, Wonkyu Kim.
Jérémy Compostella uploaded patch set #5 to this change.
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
Intel Firmware Support Package 2.4 specification brings some
significant changes compared to version 2.3 (cf. documents 736809 and
644852 respectively):
1. It supports FSP-M multi-phase init. Some fields have been added to
the FSP header data structure for this purpose.
2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be
used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively.
3. It support 64-bits FSP but 64-bits support will be provided by
subsequent patch.
Note that similarly to what is done for silicon initialization,
timestamps and post-codes are used during the memory initialization
multi-phase. However, since post-codes are in short supply, memory and
silicon multi-phase init share the same post-codes.
Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
---
M src/commonlib/include/commonlib/console/post_codes.h
M src/commonlib/include/commonlib/timestamp_serialized.h
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/intel/fsp2_0/include/fsp/util.h
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/drivers/intel/fsp2_0/upd_display.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/meteorlake/fsp_params.c
M src/soc/intel/tigerlake/fsp_params.c
M util/cbfstool/eventlog.c
13 files changed, 128 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/5
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