8 comments:
File src/mainboard/advantech/som4461/Kconfig:
Patch Set #1, Line 26: select HAVE_PIRQ_TABLE
This option refers to mainboard-specific code you have here. If you have not changed irq_tables. […]
drop this line
File src/mainboard/advantech/som4461/devicetree.cb:
are you sure?
Patch Set #1, Line 31: device pci 02.1 on end # display controller
Please what is the ID of this device ?
0x27a6 or 0x2776?
File src/mainboard/advantech/som4461/hda_verb.c:
see https://www.coreboot.org/Motherboard_Porting_Guide :
for x in /sys/class/sound/card0/hw*; do cat "$x/init_pin_configs" > pin_"$(basename "$x")"; done
for x in /proc/asound/card0/codec#*; do cat "$x" > "$(basename "$x")"; done
File src/mainboard/advantech/som4461/irq_tables.c:
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*18, /* There can be total 18 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x27b0, /* Device */
0, /* miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xf, /* u8 checksum. */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe?
drop this file ...
File src/mainboard/advantech/som4461/mptable.c:
his file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <device/pci.h>
#include <arch/smp/mpspec.h>
#include <arch/ioapic.h>
#include <string.h>
#include <stdint.h>
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
drop this file ...
File src/mainboard/advantech/som4461/romstage.c:
/* Disable unused devices */
RCBA32(FD) |= FD_INTLAN;
are you sure?
//lpc47m15x_enable_serial(PME_DEV, 0x680);
//lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
remove
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