Furquan Shaikh submitted this change.
hatch: enable genesis PCIe/USB devices
Updates PCIe registers and GPIO CLKREQ lines to match the schematic.
BUG=b:173566597,b:173567124,b:173566890
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: Ibf519b812022839f749e503436f097d3b48c4383
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/mainboard/google/hatch/variants/genesis/gpio.c
M src/mainboard/google/hatch/variants/genesis/overridetree.cb
2 files changed, 74 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c
index 5a911fc..a095da1 100644
--- a/src/mainboard/google/hatch/variants/genesis/gpio.c
+++ b/src/mainboard/google/hatch/variants/genesis/gpio.c
@@ -14,6 +14,16 @@
/* B5 : LAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+ /* B6 : M2_SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ /* B7 : M2_TPU0_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+ /* B8 : CLK_PCIE_REQ3 (not connected) */
+ PAD_NC(GPP_B8, NONE),
+ /* B9 : M2_TPU1_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ /* B10 : M2_WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
/* C0 : SMBCLK */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb
index 835a8aa..1c05f52 100644
--- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb
@@ -185,13 +185,51 @@
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
- # PCIe port 11 (x2) for NVMe hybrid storage devices
- register "PcieRpEnable[10]" = "1"
- register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
+ # PCIe port 8 for WLAN
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ # Uses CLK SRC 5
+ register "PcieClkSrcUsage[5]" = "7"
+ register "PcieClkSrcClkReq[5]" = "5"
+
+ # PCIe port 9 for TPU #0
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ # RP 9 uses CLK SRC 2
+ register "PcieClkSrcUsage[2]" = "8"
+ register "PcieClkSrcClkReq[2]" = "2"
+
+ # PCIe port 10 for TPU #1
+ register "PcieRpEnable[9]" = "1"
+ register "PcieRpLtrEnable[9]" = "1"
+ # RP 10 uses CLK SRC 4
+ register "PcieClkSrcUsage[4]" = "9"
+ register "PcieClkSrcClkReq[4]" = "4"
+
+ # PCIe port 11 (x2) for NVMe hybrid storage devices
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+ # RP 11 uses CLK SRC 1
+ register "PcieClkSrcUsage[1]" = "10"
+ register "PcieClkSrcClkReq[1]" = "1"
+ # Disable the remaining port 12
+ register "PcieRpEnable[11]" = "0"
+
+ # PCIe port 13 for i350 NIC (x4)
+ register "PcieRpEnable[12]" = "1"
+ register "PcieRpLtrEnable[12]" = "1"
+ # RP 13 uses CLK SRC 3
+ register "PcieClkSrcUsage[3]" = "12"
+ # RP 13 does not use a source clock request line
+ # Disable the remaining ports 14-16
+ register "PcieRpEnable[13]" = "0"
+ register "PcieRpEnable[14]" = "0"
+ register "PcieRpEnable[15]" = "0"
+
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"
@@ -333,15 +371,13 @@
device usb 3.3 on end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Rear Left""
- register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(1, 0)"
- device usb 3.4 on end
+ # USB3 Port 5 is not populated
+ device usb 3.4 off end
end
chip drivers/usb/acpi
- register "desc" = ""USB3 Type-A Rear Middle""
+ register "desc" = ""USB3 M.2 HDMI-to-USB""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(1, 1)"
+ register "group" = "ACPI_PLD_GROUP(2, 0)"
device usb 3.5 on end
end
end
@@ -383,8 +419,8 @@
end
end #I2C #4
device pci 1a.0 on end # eMMC
- device pci 1c.6 on
- chip drivers/net
+ device pci 1c.6 on # PCI Express Port 7 (LAN)
+ chip drivers/net # RTL8111H Ethernet NIC
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)"
@@ -394,8 +430,24 @@
register "device_index" = "0"
device pci 00.0 on end
end
- end # RTL8111H Ethernet NIC
+ end
+ device pci 1c.7 on # PCI Express Port 8 (WLAN)
+ register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
+ end
+ device pci 1d.0 on # PCI Express Port 9 (TPU)
+ register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
+ end
+ device pci 1d.1 on # PCI Express Port 10 (TPU)
+ register "PcieRpSlotImplemented[9]" = "1" # M.2 Slot
+ end
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+ device pci 1d.3 off end # PCI Express Port 12 (non-root)
+ device pci 1d.4 on # PCI Express Port 13 (X4 i350 NIC)
+ register "PcieRpSlotImplemented[12]" = "0" # Built-in
+ end
+ device pci 1d.5 off end # PCI Express Port 14 (non-root)
+ device pci 1d.6 off end # PCI Express Port 15 (non-root)
+ device pci 1d.7 off end # PCI Express Port 16 (non-root)
device pci 1e.3 off end # GSPI #1
end
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