Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson.
Felix Held has uploaded this change for review.
soc/amd/picasso: move APOB NV cache to common code
Also rename mrc_cache to apob_cache.
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4877b05443452c7409006c1656e9d574e93150a0
---
A src/soc/amd/common/block/apob/Kconfig
A src/soc/amd/common/block/apob/Makefile.inc
R src/soc/amd/common/block/apob/apob_cache.c
A src/soc/amd/common/block/include/amdblocks/apob_cache.h
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
D src/soc/amd/picasso/include/soc/mrc_cache.h
M src/soc/amd/picasso/romstage.c
8 files changed, 24 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/51267/1
diff --git a/src/soc/amd/common/block/apob/Kconfig b/src/soc/amd/common/block/apob/Kconfig
new file mode 100644
index 0000000..b0cca51
--- /dev/null
+++ b/src/soc/amd/common/block/apob/Kconfig
@@ -0,0 +1,5 @@
+config SOC_AMD_COMMON_BLOCK_APOB
+ bool
+ help
+ Select this option to add firmware support for the non-volatile APOB
+ cache to the build.
diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc
new file mode 100644
index 0000000..16baf81
--- /dev/null
+++ b/src/soc/amd/common/block/apob/Makefile.inc
@@ -0,0 +1,3 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y)
+romstage-y += apob_cache.c
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB
diff --git a/src/soc/amd/picasso/mrc_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
similarity index 97%
rename from src/soc/amd/picasso/mrc_cache.c
rename to src/soc/amd/common/block/apob/apob_cache.c
index 24d86e0..6b31143 100644
--- a/src/soc/amd/picasso/mrc_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -1,12 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
+#include <amdblocks/apob_cache.h>
#include <assert.h>
#include <boot_device.h>
#include <commonlib/region.h>
#include <console/console.h>
#include <fmap.h>
-#include <soc/mrc_cache.h>
#include <spi_flash.h>
#include <stdint.h>
#include <string.h>
@@ -95,7 +95,7 @@
}
/* Save APOB buffer to flash */
-void soc_update_mrc_cache(void)
+void soc_update_apob_cache(void)
{
struct apob_base_header *apob_rom;
struct region_device write_rdev;
@@ -159,7 +159,7 @@
return get_apob_from_nv_region(®ion);
}
-void *soc_fill_mrc_cache(void)
+void *soc_fill_apob_cache(void)
{
/* If this is non-S3 boot, then use the APOB data placed by PSP in DRAM. */
if (!acpi_is_wakeup_s3())
diff --git a/src/soc/amd/common/block/include/amdblocks/apob_cache.h b/src/soc/amd/common/block/include/amdblocks/apob_cache.h
new file mode 100644
index 0000000..1d29ddc
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/apob_cache.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef AMD_BLOCK_APOB_CACHE_H
+#define AMD_BLOCK_APOB_CACHE_H
+
+void *soc_fill_apob_cache(void);
+void soc_update_apob_cache(void);
+
+#endif /* AMD_BLOCK_APOB_CACHE_H */
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index dba95b6..ea9ee5b 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -28,6 +28,7 @@
select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_AOAC
+ select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_GRAPHICS
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index c8cc458..5ef47af 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -24,7 +24,6 @@
romstage-y += gpio.c
romstage-y += reset.c
romstage-y += uart.c
-romstage-y += mrc_cache.c
verstage-y += i2c.c
verstage_x86-y += gpio.c
diff --git a/src/soc/amd/picasso/include/soc/mrc_cache.h b/src/soc/amd/picasso/include/soc/mrc_cache.h
deleted file mode 100644
index c7fcedb..0000000
--- a/src/soc/amd/picasso/include/soc/mrc_cache.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#ifndef AMD_PICASSO_MRC_CACHE_H
-#define AMD_PICASSO_MRC_CACHE_H
-
-void *soc_fill_mrc_cache(void);
-void soc_update_mrc_cache(void);
-
-#endif /* AMD_PICASSO_MRC_CACHE_H */
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index c085a53..ecee4d3 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -3,6 +3,7 @@
#include <arch/cpu.h>
#include <acpi/acpi.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
#include <cbmem.h>
#include <cpu/x86/cache.h>
@@ -14,7 +15,6 @@
#include <program_loading.h>
#include <elog.h>
#include <soc/acpi.h>
-#include <soc/mrc_cache.h>
#include <soc/pci_devs.h>
#include <types.h>
#include "chip.h"
@@ -92,7 +92,7 @@
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
const struct soc_amd_picasso_config *config = config_of_soc();
- mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_mrc_cache();
+ mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
@@ -153,7 +153,7 @@
post_code(0x43);
fsp_memory_init(acpi_is_wakeup_s3());
- soc_update_mrc_cache();
+ soc_update_apob_cache();
memmap_stash_early_dram_usage();
To view, visit change 51267. To unsubscribe, or for help writing mail filters, visit settings.