Sergey Larin has uploaded this change for review.
src/superio: Add it8987e
Add support for IT8987E SuperIO. Based on it8528e.
Currently untested.
Signed-off-by: cerg2010cerg2010 <cerg2010cerg2010@mail.ru>
Change-Id: I3e39be986ffbdebe873ff9b9dbc6902ed1ceaf6f
---
A src/superio/ite/it8987e/Kconfig
A src/superio/ite/it8987e/Makefile.inc
A src/superio/ite/it8987e/it8987e.h
A src/superio/ite/it8987e/superio.c
4 files changed, 135 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/38253/1
diff --git a/src/superio/ite/it8987e/Kconfig b/src/superio/ite/it8987e/Kconfig
new file mode 100644
index 0000000..b8e3258
--- /dev/null
+++ b/src/superio/ite/it8987e/Kconfig
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_ITE_IT8987E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
diff --git a/src/superio/ite/it8987e/Makefile.inc b/src/superio/ite/it8987e/Makefile.inc
new file mode 100644
index 0000000..01e4d3e
--- /dev/null
+++ b/src/superio/ite/it8987e/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8987E) += superio.c
diff --git a/src/superio/ite/it8987e/it8987e.h b/src/superio/ite/it8987e/it8987e.h
new file mode 100644
index 0000000..4e265df
--- /dev/null
+++ b/src/superio/ite/it8987e/it8987e.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_ITE_IT8987E_H
+#define SUPERIO_ITE_IT8987E_H
+
+#define IT8987E_SWUC 0x04 /* System Wake-Up */
+#define IT8987E_KBCM 0x05 /* PS/2 mouse */
+#define IT8987E_KBCK 0x06 /* PS/2 keyboard */
+#define IT8987E_IR 0x0a /* Consumer IR */
+#define IT8987E_SMFI 0x0f /* Shared Memory/Flash Interface */
+#define IT8987E_RTCT 0x10 /* RTC-like Timer */
+#define IT8987E_PMC1 0x11 /* Power Management Channel 1 */
+#define IT8987E_PMC2 0x12 /* Power Management Channel 2 */
+#define IT8987E_SSPI 0x13 /* Serial Peripheral Interface */
+#define IT8987E_PECI 0x14 /* Platform EC Interface */
+#define IT8987E_PMC3 0x17 /* Power Management Channel 3 */
+#define IT8987E_PMC4 0x18 /* Power Management Channel 4 */
+#define IT8987E_PMC5 0x19 /* Power Management Channel 5 */
+
+
+#endif /* SUPERIO_ITE_IT8987E_H */
diff --git a/src/superio/ite/it8987e/superio.c b/src/superio/ite/it8987e/superio.c
new file mode 100644
index 0000000..dce7a6f
--- /dev/null
+++ b/src/superio/ite/it8987e/superio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Sergey Larin <cerg2010cerg2010@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+
+#include "it8987e.h"
+
+static void it8987e_init(struct device *dev)
+{
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8987e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8987E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
+ { NULL, IT8987E_KBCM, PNP_IRQ0, },
+ { NULL, IT8987E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
+ { NULL, IT8987E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, },
+ { NULL, IT8987E_SMFI, PNP_IO0 | PNP_IRQ0 | PNP_MSC4, 0xfff0, },
+ { NULL, IT8987E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0
+ | PNP_MSC0 | PNP_MSC1 | PNP_MSC2,
+ 0xfffe, 0xfffe, 0xfffe, 0xfffe},
+ { NULL, IT8987E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 | PNP_MSC0,
+ 0x07fc, 0x07fc, 0xfff0 },
+ { NULL, IT8987E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 },
+ { NULL, IT8987E_PECI, PNP_IO0, 0xfff8 },
+ { NULL, IT8987E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+ { NULL, IT8987E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
+ 0x07ff, 0x07ff },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8987e_ops = {
+ CHIP_NAME("ITE IT8987E Super I/O")
+ .enable_dev = enable_dev,
+};
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