Jonathan A. Kollasch (jakllsch@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12304
-gerrit
commit 768b4b09bb4593f1a16e572c8f10b56ca93c614b Author: Jonathan A. Kollasch jakllsch@kollasch.net Date: Tue Nov 3 10:06:38 2015 -0600
Initial Sun Ultra 40 M2 board port
Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30 Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net --- src/mainboard/sunw/ultra40m2/Kconfig | 18 +++--- src/mainboard/sunw/ultra40m2/Kconfig.name | 4 +- src/mainboard/sunw/ultra40m2/board_info.txt | 7 ++- src/mainboard/sunw/ultra40m2/devicetree.cb | 89 ++++++----------------------- src/mainboard/sunw/ultra40m2/resourcemap.c | 6 +- src/mainboard/sunw/ultra40m2/romstage.c | 11 +--- 6 files changed, 44 insertions(+), 91 deletions(-)
diff --git a/src/mainboard/sunw/ultra40m2/Kconfig b/src/mainboard/sunw/ultra40m2/Kconfig index b5e51c5..2913ae8 100644 --- a/src/mainboard/sunw/ultra40m2/Kconfig +++ b/src/mainboard/sunw/ultra40m2/Kconfig @@ -1,4 +1,4 @@ -if BOARD_NVIDIA_L1_2PVV +if BOARD_SUNW_ULTRA40M2
config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -10,19 +10,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA - select SUPERIO_WINBOND_W83627EHG + select SUPERIO_SMSC_DME1737 select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select LIFT_BSP_APIC_ID - select BOARD_ROMSIZE_KB_512 + select BOARD_ROMSIZE_KB_1024 select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE
config MAINBOARD_DIR string - default nvidia/l1_2pvv + default sunw/ultra40m2
config DCACHE_RAM_BASE hex @@ -46,7 +46,7 @@ config MCP55_NUM
config MAINBOARD_PART_NUMBER string - default "l1_2pvv" + default "Ultra 40 M2"
config MAX_CPUS int @@ -70,6 +70,10 @@ config IRQ_SLOT_COUNT
config MCP55_PCI_E_X_0 int - default 2 + default 1 + +config MCP55_PCI_E_X_1 + int + default 1
-endif # BOARD_NVIDIA_L1_2PVV +endif # BOARD_SUNW_ULTRA40M2 diff --git a/src/mainboard/sunw/ultra40m2/Kconfig.name b/src/mainboard/sunw/ultra40m2/Kconfig.name index 40dffc6..f6bc551 100644 --- a/src/mainboard/sunw/ultra40m2/Kconfig.name +++ b/src/mainboard/sunw/ultra40m2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_NVIDIA_L1_2PVV - bool "l1_2pvv" +config BOARD_SUNW_ULTRA40M2 + bool "Ultra 40 M2" diff --git a/src/mainboard/sunw/ultra40m2/board_info.txt b/src/mainboard/sunw/ultra40m2/board_info.txt index b351b8e..b68555c 100644 --- a/src/mainboard/sunw/ultra40m2/board_info.txt +++ b/src/mainboard/sunw/ultra40m2/board_info.txt @@ -1 +1,6 @@ -Category: eval +Board URL: http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html +Board name: Ultra 40 M2 +Category: desktop +ROM package: PLCC +ROM protocol: LPC +ROM socketed: y diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index 5709db7..bf89fee 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -5,66 +5,44 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit + subsystemid 0x108e 0x6676 inherit chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O + chip superio/smsc/dme1737 # Super I/O device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel port + device pnp 2e.3 off # Parallel port io 0x60 = 0x378 irq 0x70 = 7 + drq 0x74 = 2 end - device pnp 2e.2 on # Com1 + device pnp 2e.4 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off # Com2 + device pnp 2e.5 off # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # PS/2 keyboard & mouse + device pnp 2e.7 on # PS/2 (connectors not populated) io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 + device pnp 2e.a on + io 0x60 = 0x600 end end + # There's also an Akom AK2001 7-segment port 0x80 decoder on + # and Infineon SLB9635TT12 TPM on this LPC bus. end device pci 1.1 on # SM 0 chip drivers/generic/generic # DIMM 0-0-0 @@ -93,41 +71,17 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 on end # PCI device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC + device pci 8.0 off end # NIC + device pci 9.0 off end # NIC device pci a.0 on end # PCI E 5 device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 @@ -137,12 +91,8 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end - device pci 18.0 on end # Link 1 device pci 18.0 on # Link 2 == LDT 2 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT @@ -153,7 +103,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci 4.0 off end # IDE device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 + device pci 5.2 off end # SATA 2 device pci 6.0 off end # PCI device pci 6.1 off end # AZA device pci 8.0 on end # NIC @@ -162,14 +112,11 @@ chip northbridge/amd/amdk8/root_complex # Root complex device pci b.0 off end # PCI E 4 device pci c.0 off end # PCI E 3 device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 + device pci e.0 off end # PCI E 1 device pci f.0 on end # PCI E 0 register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end device pci 18.1 on end diff --git a/src/mainboard/sunw/ultra40m2/resourcemap.c b/src/mainboard/sunw/ultra40m2/resourcemap.c index 2950687..e46a253 100644 --- a/src/mainboard/sunw/ultra40m2/resourcemap.c +++ b/src/mainboard/sunw/ultra40m2/resourcemap.c @@ -17,6 +17,7 @@
static void setup_mb_resource_map(void) { +#if 0 static const unsigned int register_values[] = { /* Careful set limit registers before base registers which contain the enables */ /* DRAM Limit i Registers @@ -194,7 +195,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000, +// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007010, // PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff020, // need to talk to ANALOG of second CK804 to release PCI E reset PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -265,7 +266,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000003, /* link 0 of cpu 0 --> Nvidia MCP55 Pro */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000103, /* link 1 of cpu 0 --> Nvidia MCP55 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f400203, /* link 2 of cpu 0 --> nvidia io55 */ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, @@ -275,4 +276,5 @@ static void setup_mb_resource_map(void) int max; max = ARRAY_SIZE(register_values); setup_resource_map(register_values, max); +#endif } diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 4186cc7..d225f59 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -32,14 +32,13 @@ #include "lib/delay.c" #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1)
static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -114,13 +113,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); - setup_mb_resource_map();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + dme1737_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
/* Halt if there was a built in self test failure */