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3 comments:
File src/arch/riscv/ramdetect.c:
Patch Set #9, Line 21: #define insn_size 4
Is this true in an era of compact instruction extension? I no longer know. […]
we can't. to be really sure we'd have to read the instruction from memory. so this is a hack that works as long as we have 4 byte instructions.
Can we ensure we never build with compact instrutions enabled? I'd be fine with that.
see above.
Patch Set #9, Line 35: uintptr_t addr = dram_start + (size * MiB) - sizeof(uint32_t);
Should we make sure dram_start is 32-bit aligned, in case of someone doing something silly? it would […]
dram_start is coming from the linker file and we assume that memory is usually aligned, if not I'd rather have an exception during probing, I think.
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