Attention is currently required from: Alicja Michalska, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, yuchi.chen@intel.com.
Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email )
Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85170/comment/48164917_ccf9455c?usp... : PS4, Line 15: from advertising wrong GSI addresses.
Will the soc_get_ioapic_info and XEON_SP_HAVE_IIO_IOAPIC got totally removed in a later patch?
Yes, it should be dropped on CPX as well. Though the only board that uses CPX is single socket and thus does have a linear GSI address space. It doesn't need this code, but could reuse it.
File src/soc/intel/xeon_sp/lpc_gen1.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/731796bb_2fcd63cb?usp... : PS4, Line 14: register_new_ioapic_gsi0(IO_APIC_ADDR);
Will ioapic0 be created with a dev object as well? (and if yes, will the register_new_ioapic_gsi0 ca […]
Currently it's not created as dev object. When CONFIG_ACPI_COMMON_MADT_IOAPIC is selected ioapic 0 at IO_APIC_ADDR will always be added to MADT. The code could be changed to only support dev objects though.
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/08ede173_8c4c9c3c?usp... : PS4, Line 47: }
So each IIO IOAPIC with 8 GSIs, and the dn. […]
that is correct.
https://review.coreboot.org/c/coreboot/+/85170/comment/d8fa0e59_d887b8fc?usp... : PS4, Line 49: i
Is this defined in somewhere?
#include <arch/ioapic.h>
https://review.coreboot.org/c/coreboot/+/85170/comment/b2639f27_5766fc81?usp... : PS4, Line 61: .enable_resources = pci_dev_enable_resources,
Should we use pci_bus_enable_resources?
it's a PCI endpoint device