Shelley Chen has uploaded this change for review.
soc/qualcomm/common: Add strict_check flags to clock_configure()
Add strict parameter to clock_configure(). When this parameter is set
to true, clock_configure() will try to find an exact match to the
clock frequency given. If exact match cannot be found, then will
throw an assert error.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and try to set SPI frequency to number not
supported. Ensure assert is seen.
Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc
Signed-off-by: Shelley Chen <shchen@google.com>
---
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7180/clock.c
M src/soc/qualcomm/sc7280/clock.c
4 files changed, 30 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/1
diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index e06a954..4a2b0a8 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -90,8 +90,8 @@
/* Clock Root clock Generator Operations */
enum cb_err clock_configure(struct clock_rcg *clk,
- struct clock_freq_config *clk_cfg, uint32_t hz,
- uint32_t num_perfs)
+ struct clock_freq_config *clk_cfg, uint32_t hz,
+ uint32_t num_perfs, bool strict)
{
uint32_t reg_val, idx;
@@ -99,6 +99,10 @@
if (hz <= clk_cfg[idx].hz)
break;
+ /* If strict flag is set, check if found exact match */
+ if (strict && hz != clk_cfg[idx].hz)
+ assert("ERROR: No exact match found for QSPI clk frequency!\n");
+
reg_val = (clk_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) |
(clk_cfg[idx].div << CLK_CTL_CFG_SRC_DIV_SHFT);
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index 0911827..82464cf 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -145,8 +145,22 @@
void clock_reset_bcr(void *bcr_addr, bool assert);
+/*
+ * clock_configure(): Configure the clock at the given clock speed (hz). If hz
+ * does not match any entries in the clk_cfg array, will round up to the next
+ * highest clock frequency. If strict=1, will throw an assert error if there is
+ * no frequency match in clk_cfg.
+ *
+ * @param clk struct clock_rcg pointer (root clock generator)
+ * @param clk_cfg Array with possible clock configurations
+ * @param hz frequency of clock to set
+ * @param num_perfs size of clock array
+ * @param strict Flag to enable strict checking. If the given frequency
+ * in hz does not match any entry in clk_cfg array, will
+ * throw an assert error.
+ */
enum cb_err clock_configure(struct clock_rcg *clk, struct clock_freq_config *clk_cfg,
- uint32_t hz, uint32_t num_perfs);
+ uint32_t hz, uint32_t num_perfs, bool strict);
void clock_configure_dfsr_table(int qup, struct clock_freq_config *clk_cfg,
uint32_t num_perfs);
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c
index 5741c54..ae5f43d 100644
--- a/src/soc/qualcomm/sc7180/clock.c
+++ b/src/soc/qualcomm/sc7180/clock.c
@@ -119,7 +119,7 @@
{
clock_configure(&gcc->qspi_core,
qspi_core_cfg, hz,
- ARRAY_SIZE(qspi_core_cfg));
+ ARRAY_SIZE(qspi_core_cfg), true);
clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
clock_enable(&gcc->qspi_core_cbcr);
}
@@ -215,7 +215,7 @@
mdss_clk_cfg.d_2 = d_2;
return clock_configure((struct clock_rcg *)mdss_clock[clk_type],
- &mdss_clk_cfg, 0, 0);
+ &mdss_clk_cfg, 0, 0, false);
}
int mdss_clock_enable(enum mdss_clock clk_type)
diff --git a/src/soc/qualcomm/sc7280/clock.c b/src/soc/qualcomm/sc7280/clock.c
index 746035c..68b5909 100644
--- a/src/soc/qualcomm/sc7280/clock.c
+++ b/src/soc/qualcomm/sc7280/clock.c
@@ -266,7 +266,8 @@
{
clock_configure(&gcc->qspi_core,
qspi_core_cfg, hz,
- ARRAY_SIZE(qspi_core_cfg));
+ ARRAY_SIZE(qspi_core_cfg),
+ true);
clock_enable(&gcc->qspi_cnoc_ahb_cbcr);
clock_enable(&gcc->qspi_core_cbcr);
}
@@ -307,7 +308,7 @@
clock_configure_enable_gpll(&gpll10_cfg, true, 9);
}
clock_configure((struct clock_rcg *)&gcc->sdcc1, sdcc1_core_cfg,
- hz, ARRAY_SIZE(sdcc1_core_cfg));
+ hz, ARRAY_SIZE(sdcc1_core_cfg), false);
clock_enable(&gcc->sdcc1_ahb_cbcr);
clock_enable(&gcc->sdcc1_apps_cbcr);
} else if (sdcc == SDCC2_CLK) {
@@ -326,7 +327,7 @@
clock_configure_enable_gpll(&gpll9_cfg, true, 8);
}
clock_configure((struct clock_rcg *)&gcc->sdcc2, sdcc2_core_cfg,
- hz, ARRAY_SIZE(sdcc2_core_cfg));
+ hz, ARRAY_SIZE(sdcc2_core_cfg), false);
clock_enable(&gcc->sdcc2_ahb_cbcr);
clock_enable(&gcc->sdcc2_apps_cbcr);
}
@@ -422,11 +423,11 @@
case MDSS_CLK_EDP_PIXEL:
case MDSS_CLK_PCLK0:
return clock_configure((struct clock_rcg *)
- mdss_clock_mnd[clk_type],
- &mdss_clk_cfg, hz, 0);
+ mdss_clock_mnd[clk_type],
+ &mdss_clk_cfg, hz, 0, false);
default:
return clock_configure(mdss_clock[clk_type],
- &mdss_clk_cfg, hz, 0);
+ &mdss_clk_cfg, hz, 0, false);
}
}
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