Richard Spiegel has uploaded this change for review.
Documentation/mainboard/amd: Add padmelon doucumentation and images
Extract publicly available information and pictures from padmelon manual,
and make them available to coreboot community. Add information on
programming SPI.
BUG=none.
TEST=none.
Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
---
A Documentation/mainboard/amd/Padmelon.md
A Documentation/mainboard/amd/padmelon/padmelon.jpg
A Documentation/mainboard/amd/padmelon/padmelon_components.jpg
A Documentation/mainboard/amd/padmelon/padmelon_io.jpg
A Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg
M Documentation/soc/amd/index.md
A Documentation/soc/amd/merlinfalcon.md
7 files changed, 95 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/34493/1
diff --git a/Documentation/mainboard/amd/Padmelon.md b/Documentation/mainboard/amd/Padmelon.md
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index 0000000..2868b05
--- /dev/null
+++ b/Documentation/mainboard/amd/Padmelon.md
@@ -0,0 +1,66 @@
+# Padmelon board
+
+## Specs (Merlin Falcon)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+ Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot code
+ is specific for Merlin Falcon SOC. Some specs change if not Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0* ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* Supports 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Picture padmelon components mistakes.
+
+The picture was extracted from manual, however, the numbering on the padmelon board is misplaced.
+Of real importance is that (6) is actually the dediprog header to flash the BIOS.
+(16) is actually 2 mux chips that acts like a bridge between the SPI and the CPU or the dediprog
+header. The bridge will connect the SPI to the header if and only if no power is applied to the CPU,
+thugh the board itself can be connected to a power supply that is connected to AC. With or without
+AC connected, provided CPU is not powered, SPI can be programmed using dediprog. Once CPU is powered,
+dediprog is protected from harm (even if still connected to the header) because the mux will float
+the pins. The mux should be the first place to be investigated if you are unable to program the SPI.
+
+## Flashing coreboot
+
++---------------------+--------------------+
+| Type | Value |
++=====================+====================+
+| Socketed flash | no |
++---------------------+--------------------+
+| Model | Macronix MX256435E |
++---------------------+--------------------+
+| Size | 8 MiB |
++---------------------+--------------------+
+| In circuit flashing | no, use dediprog |
++---------------------+--------------------+
+| Package | SOIC-8 |
++---------------------+--------------------+
+| Write protection | No |
++---------------------+--------------------+
+```
+
+## Technology
+
++---------------+------------------------------+
+| SoC | :doc:`../../soc/amd/index` |
++---------------+------------------------------+
+| CPU | Merlin Falcon SOC |
++---------------+------------------------------+
+
+## Pictures
+
++----------------------------+----------------------------------------+
+|padmelon.jpg | Motherboard with components identified |
++----------------------------+----------------------------------------+
+|padmelon_components.jpg | Identifying components |
++----------------------------+----------------------------------------+
+|padmelon_io.jpg | Back panel picture |
++----------------------------+----------------------------------------+
+|padmelon_io_description.jpg | Back panel description |
++----------------------------+----------------------------------------+
diff --git a/Documentation/mainboard/amd/padmelon/padmelon.jpg b/Documentation/mainboard/amd/padmelon/padmelon.jpg
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diff --git a/Documentation/mainboard/amd/padmelon/padmelon_components.jpg b/Documentation/mainboard/amd/padmelon/padmelon_components.jpg
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diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg
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+++ b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg
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diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io_description.jpg
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diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md
index 7945b48..84d070b 100644
--- a/Documentation/soc/amd/index.md
+++ b/Documentation/soc/amd/index.md
@@ -4,5 +4,6 @@
## Technology
+- [Merlin Falcon](merlinfalcon.md)
- [Family 17h](family17h.md)
diff --git a/Documentation/soc/amd/merlinfalcon.md b/Documentation/soc/amd/merlinfalcon.md
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+++ b/Documentation/soc/amd/merlinfalcon.md
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+# AMD Merlin Falcon in coreboot
+
+## Abstract
+
+Merlin Falcon is a family 15h Models 60-6F SOC, more specifically, 00660F01.
+
+## Introduction
+
+Family 15h products are x86-based designs. This documentation assumes
+familiarity with x86, its reset state and its early initialization
+requirements.
+
+AMD has historically required an NDA for access to the PSP
+specification<sup>1</sup>. coreboot relies on util/amdfwtool to build
+the structures and add various other firmware to the final image.
+
+Support in coreboot for modern AMD products is based on AMD’s
+reference code: AMD Generic Encapsulated Software Architecture
+(AGESA<sup>TM</sup>). AGESA contains the technology for enabling DRAM,
+configuring proprietary core logic, assistance with generating ACPI
+tables, and other features.
+
+## Additional Definitions
+
+* PSP, Platform Security Processor: Onboard ARM processor that runs
+alongside the main x86 processor; may be viewed as analogous to the
+Intel<sup>R</sup> Management Engine
+* FCH, Fusion Control Hub, the logical southbridge within the SOC
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